Switched-capacitor structures with enhanced isolation

• US 6,859,159 B2
• Filed: 06/18/2003
• Issued: 02/22/2005
• Est. Priority Date: 06/18/2002
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Michalski, Christopher
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Mai, Lam T.
• Application Number:
  US10/463,933
• Publication Number:
  US 20040070917A1
• Time in Patent Office: 615 Days
• Field of Search: 341/172, 341/161, 341/143, 341/122, 341/136
• US Class Current: 341/172
• CPC Class Codes: H03H 19/004 Switched capacitor networks
• CPC Class Codes: H03M 1/08 of noise H03M1/0617 takes precedence
• CPC Class Codes: H03M 1/168 and delivering the same number of bits
• CPC Class Codes: H03M 1/442 using switched capacitors

Abstract

Switched-capacitor structures are provided that reduce distortion and noise in their processed signals because they increase isolation between structural elements and ensure that selected elements are securely turned off in one mode and quickly turned on in another mode.

Claims

1. A switched-capacitor stage that operates in a sample mode and a transfer mode, the stage comprising:

first and second sample switches;

a buffer transistor having a control terminal coupled to said first sample switch and also having a current terminal;

a sample capacitor coupled between said current terminal and second sample switch to thereby receive a sample charge Q_s when said first and second sample switches are closed in said sample mode; and

first and second transfer switches that are respectively coupled to said control and said current terminals to bias off said buffer transistor and transfer at least a portion of said sample charge Q_s to said transfer capacitor when said first and second transfer switches are closed in said transfer mode.

2. The stage of claim 1, wherein said first and second sample switches and said first and second transfer switches are metal-oxide semiconductor transistors.

3. The stage of claim 1, wherein said control terminal is a base and said current terminal is an emitter.

4. The stage of claim 1, further including:

a differential amplifier coupled to said sample capacitor and said second transfer switch; and

a transfer capacitor coupled about said differential amplifier.

5. A pipelined analog-to-digital converter that converts an analog signal to a corresponding digital signal, comprising:

a sampler that provides a sample signal in response to said analog signal;

an initial converter stage that processes said sample signal to provide a residue signal and respective bits of said digitalsignal; and

at least one successive converter stage that processes a preceding residue signal to provide a successive residue signal and respective bits of said digital signal wherein a final converter stage only provides said respective bits;

and wherein said sampler operates in a sample mode and a transfer mode and includes;

a) first and second sample switches;

b) a buffer transistor having a control terminal coupled to said first sample switch and also having a current terminal;

c) a sample capacitor coupled between said current terminal and second sample switch to thereby receive a sample charge Qs when said first and second sample switches are closed in said sample mode; and

d) first and second transfer switches that are respectively coupled to said control and said current terminals to bias off said buffer transistor and transfer at least a portion of said sample charge Q_s to said transfer capacitor when said first and second transfer switches are closed in said transfer mode.

6. The converter of claim 5, wherein said first and second sample switches and said first and second transfer switches are metal-oxide semiconductor transistors.

7. The converter of claim 5, wherein said control terminal is a base and said current terminal is an emitter.

8. The converter of claim 5, further including:

a differential amplifier coupled to said sample capacitor and said second transfer switch; and

a transfer capacitor coupled about said differential amplifier.