RFID tag with a quadrupler or N-tupler circuit for efficient RF to DC conversion

• US 6,859,190 B2
• Filed: 06/04/2003
• Issued: 02/22/2005
• Est. Priority Date: 06/04/2002
• Status: Active Grant

• Current Assignee: Intermec IP Corporation (Honeywell International Inc.)
• Original Assignee: Intermec IP Corporation (Honeywell International Inc.)
• Inventors: Heinrich, Harley Kent, Pillai, Vijay, Martinez, Rene D.
• Primary Examiner(s): Wimer, Michael C.
• Application Number:
  US10/455,757
• Publication Number:
  US 20030222763A1
• Time in Patent Office: 629 Days
• Field of Search: 343/860, 343/895, 343/866, 343/867, 343/742, 340/572.4, 340/572.5, 340/572.7, 342/42, 342/44
• US Class Current: 343/860
• CPC Class Codes: G06K 19/0701 at least one of the integrated circuit chips comprising an arrangement for power management
• CPC Class Codes: G06K 19/0713 the arrangement including a power charge pump
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Abstract

A multistage voltage multiplying circuit for single chip passive RF tags is provided, wherein the parasitic capacitance of the diodes of each stage of the voltage multiplying circuit is much less than the parasitic capacitance of the diodes of the preceding stage.

Claims

1. An apparatus, comprising;

a passive radio frequency (RF) transponder (Tag), comprising;

an antenna for receiving power and signals from an RF field, and for sending signals by backscattering power from the RF field;

tag electronics connected to the antenna, the tag electronics contained in a single semiconductor chip, the tag electronics for receiving signals from the antenna and for controlling the antenna impedance for sending signals;

a tag power supply in the single semiconductor chip for receiving RF power from the antenna, the tag power supply used as the sole power supply for the tag electronics;

wherein the RF power is rectified in a diode rectifier circuit, and wherein the diode rectifier circuit comprises;

at least a first diode rectifier stage for producing a DC voltage greater than the AC RF voltage produced in the antenna by the RF field, and;

at least a second diode rectifier stage for producing a voltage greater than twice the AC RF voltage produced in the antenna by the RF field;

wherein the parasitic capacitance of the second diode rectifier stage is less than 80% of the parasitic capacitance of the first diode rectifier stage.

2. The apparatus of claim 1, wherein the parasitic capacitance of the second diode rectifier stage is less than 50% of the parasitic capacitance of the first diode rectifier stage.

3. The apparatus of claim 2, wherein the parasitic capacitance of the second diode rectifier stage is less than 30% of the parasitic capacitance of the first diode rectifier stage.

4. The apparatus of claim 1, wherein the second diode rectifier stage contains a coupling capacitor which has a capacitance C_C, a parasitic capacitance C_PC, and an RF impedance Z_C, and wherein Z_C is much less than the RF impedance Z_QUAD of the diodes of the second diode rectifier stage.

5. The apparatus of claim 1, further comprising at least a third diode rectifier stage wherein the parasitic capacitance of the third diode rectifier stage is less than 50% of the parasitic capacitance of the second diode rectifier stage.