Source side self boosting technique for non-volatile memory

• US 6,859,397 B2
• Filed: 03/05/2003
• Issued: 02/22/2005
• Est. Priority Date: 03/05/2003
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Lutze, Jeffrey W., Chen, Jian, Higashitani, Masaaki, Li, Yan
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US10/379,608
• Publication Number:
  US 20040174748A1
• Time in Patent Office: 720 Days
• Field of Search: 365/185.28, 365/185.17, 365/185.18, 365/185.22, 365/185.24, 365/185.29, 365/185.03, 365/238.5, 365/195, 365/196
• US Class Current: 365/185.28
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells

Abstract

A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e.g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.

Claims

1. A method of programming a memory system, comprising:

boosting a voltage potential of a source side channel region of a first set of non-volatile storage elements, said first set of non-volatile storage elements includes a non-volatile storage element to be inhibited, said first set of non-volatile storage elements includes drain side unselected non-volatile storage elements and source side unselected non-volatile storage elements in relation to said non-volatile storage element to be inhibited, said source side unselected non-volatile storage elements include a source side neighbor and source side non-neighbors, said boosting a voltage potential includes applying an intermediate voltage signal to control gates for said source side neighbor and said source side non-neighbors for a first period of time while remaining out of communication with a source line;

applying a program voltage to a non-volatile storage element selected for programming and said non-volatile storage element to be inhibited during a second period of time after said first period of time, said non-volatile storage element selected for programming is part of a second set of non-volatile storage elements;

applying a lower voltage than said intermediate voltage to said source side neighbor during said second period of time; and

applying a pass voltage to said source side non-neighbors during said second period of time, said pass voltage is greater than said intermediate voltage.

2. A method according to claim 1, wherein:

said non-volatile storage element selected for programming is a NAND cell that is part of a first string of NAND cells;

said first set of non-volatile storage elements comprises a second string of NAND cells;

said non-volatile storage element selected for programming and said non-volatile storage element to be inhibited are both connected to a first word line; and

said step of applying a program voltage includes applying said program voltage to said first word line.

3. A method according to claim 2, wherein:

said remaining out of communication with a source line includes maintaining a select gate in an off state while applying said intermediate voltage signal, said select gate connects said second string of NAND cells with said source line.

4. A method according to claim 1, further comprising:

providing zero volts at control gates for said drain side unselected non-volatile storage elements while applying said intermediate voltage signal.

5. A method according to claim 1, further comprising:

providing zero volts at a control gate for said non-volatile storage element to be inhibited while applying said intermediate voltage signal.

6. A method according to claim 5, further comprising:

providing zero volts at control gates for said drain side unselected non-volatile storage elements while applying said intermediate voltage signal; and

providing a non-zero inhibit voltage to a bit line for said first set of non-volatile storage elements and allowing said inhibit voltage to effect a channel potential for said first set of non-volatile storage elements.

7. A method according to claim 1, wherein:

said non-volatile storage element selected for programming is a NAND cell that is part of a first string of NAND cells;

said first set of non-volatile storage elements comprises a second string of NAND cells;

said non-volatile storage element selected for programming and said non-volatile storage element to be inhibited are both connected to a first word line;

additional word lines connect to other NAND cells of said first string of NAND cells and said second string of NAND cells;

said additional word lines include source side word lines; and

said step of boosting includes applying said intermediate voltage to all of said source side word lines.

8. A method according to claim 1, wherein:

said non-volatile storage element selected for programming and said non-volatile storage element to be inhibited are flash memory devices.

9. A method according to claim 1, wherein:

said non-volatile storage element selected for programming is a NAND flash memory cell that is part of a first string of NAND cells; and

said first set of non-volatile storage elements comprise a second string of NAND cells.

10. A method according to claim 9, further comprising the steps of:

applying a first voltage to a first bit line corresponding to said first string of NAND cells; and

applying a second voltage to a second bit line corresponding to second string of NAND cells, said second voltage is greater than zero volts.

11. A method according to claim 10, wherein:

said first voltage is a ground voltage.

12. A method according to claim 1, wherein:

said non-volatile storage element selected for programming and said non-volatile storage element to be inhibited are multi-level flash memory cells.

13. A memory system, comprising:

a first set of non-volatile storage elements, said first set of non-volatile storage elements includes a non-volatile storage element to be programmed;

a second set of non-volatile storage elements, said second set of non-volatile storage elements includes a non-volatile storage element to be inhibited, said second set of non-volatile storage elements capable of having a source side channel region with a voltage potential of at least a boosted voltage potential during a programming operation, said second set of non-volatile storage elements includes drain side unselected non-volatile storage elements and source side unselected non-volatile storage elements in relation to said non-volatile storage element to be inhibited, said source side unselected non-volatile storage elements include a source side neighbor and source side non-neighbors;

a plurality of word lines, said plurality of word lines includes a first word line connected to said non-volatile storage element to be programmed and to said non-volatile storage element to be inhibited to apply a program voltage to said non-volatile storage element to be programmed and said non-volatile storage element to be inhibited during said program operation, said plurality of word lines further includes source side word lines connected to said source side unselected non-volatile storage elements to apply a pass voltage to said source side non-neighbors while said program voltage is applied to said non-volatile storage element to be inhibited, said source side word lines apply an intermediate voltage to said source side unselected non-volatile storage elements prior to applying said pass voltage, said intermediate voltage is less than said pass voltage; and

a first select gate between a source line and said first set of non-volatile storage elements and a second select gate between said source line and said second set of non-volatile storage elements, said first and second select gates configured to disconnect said source line from said first set of non-volatile storage elements and said second set of non-volatile storage elements while said source side word lines apply said intermediate voltage to said source side unselected non-volatile storage elements.

14. A memory system according to claim 13, wherein:

said first set of non-volatile storage elements comprise a first NAND string of flash memory cells; and

said second set of non-volatile storage elements comprise a second NAND string of flash memory cells.

15. A memory system according to claim 14, further comprising:

a plurality of bit lines, a first bit line of said plurality of bit lines is connected to said first NAND string, a second bit line of said plurality of bit lines is connected to said second NAND string.

16. A memory system according to claim 14, wherein:

said plurality of word lines further includes drain side word lines connected to said drain side unselected non-volatile storage elements for providing zero volts at control gates for said drain side unselected non-volatile storage elements while applying said intermediate voltage.

17. A memory system according to claim 16, wherein:

zero volts are applied on said first word line while applying said intermediate voltage.

18. A memory system according to claim 13, wherein:

a first voltage is applied on said first word line while applying said intermediate voltage, said first voltage is less than said intermediate voltage.

19. A memory system according to claim 14, wherein:

said first NAND string and said second NAND string include drain select gates receiving a select voltage of Vdd+Vtd, where Vtd is a threshold voltage for said drain select gates.

20. A method of programming a memory system, comprising:

programming non-volatile storage elements along two or more NAND strings from source side to drain side, said programming includes applying a program pulse to non-volatile storage elements selected for programming and inhibiting at a given time;

applying an intermediate voltage to source side non-neighbors in relation to non-volatile storage elements selected for inhibiting, said intermediate voltage is applied prior to applying said program pulse;

applying a lower voltage than said intermediate voltage to source side neighbors of said non-volatile storage elements selected for inhibiting while applying said intermediate voltage to source side non-neighbors; and

applying a pass voltage to said source side non-neighbors while applying said program pulse to non-volatile storage elements selected for programming and inhibiting, said pass voltage is greater than said intermediate voltage.

21. A method according to claim 20, further comprising:

coupling said NAND strings to a common source line voltage greater than zero volts.

22. A method according to claim 20, wherein:

said lower voltage is zero volts.

23. A method according to claim 20, further comprising:

applying zero volts to drain side non-volatile storage elements, with respect to said non-volatile storage elements selected for programming and inhibiting, while applying said intermediate voltage.

24. A method according to claim 20, further comprising:

applying a voltage signal lower than said intermediate voltage to said non-volatile storage elements selected for inhibiting while applying said intermediate voltage.

25. A method according to claim 20, wherein:

said non-volatile storage elements selected for programming and inhibiting are multi-level NAND flash memory devices.

26. A memory system, comprising:

a first NAND string;

a second NAND string; and

one or more managing circuits in communication with said first NAND string and said second NAND string, said one or more managing circuits capable of programming said first NAND string and said second NAND string from a source side to a drain side, said one or more managing circuits perform said programming by applying a program pulse to a non-volatile storage element to be programmed of said first NAND string and to a non-volatile storage element to be inhibited of said second NAND string, said programming further includes applying an intermediate voltage to source side non-neighbors of said non-volatile storage element to be inhibited prior to applying said program pulse, said programming further includes applying a lower voltage than said intermediate voltage to a source side neighbor of said non-volatile storage element to be inhibited and applying a pass voltage to said source side non-neighbors while applying said program pulse, said pass voltage is greater than said intermediate voltage.

27. A memory system according to claim 26, further comprising:

source select gates coupling said first NAND string and said second NAND string to a common source line voltage greater than zero volts.

28. A memory system according to claim 26, wherein:

said lower voltage is zero volts.

29. A memory system according to claim 26, wherein:

said one or more managing circuits apply a voltage lower than said intermediate voltage to drain side non-volatile storage elements, with respect to said non-volatile storage element to be inhibited, while applying said intermediate voltage.

30. A memory system according to claim 26, further comprising:

applying zero volts to said non-volatile storage element to be inhibited while applying said intermediate voltage.

31. A memory system according to claim 26, wherein:

said non-volatile storage element to be programmed is a multi-level NAND flash memory device.