Tree decoder structure particularly well-suited to interfacing array lines having extremely small layout pitch

• US 6,859,410 B2
• Filed: 11/27/2002
• Issued: 02/22/2005
• Est. Priority Date: 11/27/2002
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Crowley, Matthew P.
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US10/306,888
• Publication Number:
  US 20040100852A1
• Time in Patent Office: 818 Days
• Field of Search: 365/63, 365/230.06
• US Class Current: 365/230.06
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A tree decoder organization particularly useful for a three-dimensional memory array or any array having very small array line pitch is configured to provide a plurality of top-level decode nodes, each of which, when selected, simultaneously selects a block of array lines and couples each array line of a selected block to a respective intermediate node. Each of the top-level decode signals has a range of control which is substantially less than the extent of the intermediate nodes. In some embodiments each selected block includes more than one array line on each of at least two memory layers having array lines which exit to one side of the memory array. As a result, the large layout area requirement to generate each top-level decode node is supported by a contiguous block of array lines of the memory array.

Claims

1. An integrated circuit comprising:

a memory sub-array having a plurality of array lines on at least one layer of the memory sub-array, at least some of the array lines exiting to one side of the memory sub-array;

a tree decoder circuit associated with the memory sub-array, said tree decoder circuit comprising a top level responsive to a plurality of top-level control signals, and comprising at least a second level responsive to a plurality of second-level control signals, and further comprising a plurality of intermediate nodes between the top-level and second level each extending along the one side of the sub-array;

wherein each of the plurality of top-level control signals has a range of control which is substantially less than the extent of each intermediate node.

2. The integrated circuit as recited in claim 1 wherein the memory sub-array comprises a three-dimensional memory sub-array comprising at least two layers of array lines having at least some array lines exiting to the one side of the memory sub-array.

3. The integrated circuit as recited in claim 1 wherein each of the plurality of top-level signals selects a respective group of array lines, each respective array line of a group being coupled to a respective one of the plurality of intermediate nodes.

4. The integrated circuit as recited in claim 3 wherein unselected top-level signals couple each respective array line of an unselected group to an associated unselected bias node.

5. The integrated circuit as recited in claim 4 further comprising at least one unselected array line bias circuit for respectively generating an unselected bias voltage on at least one unselected bias node.

6. The integrated circuit as recited in claim 3 wherein each respective group comprises a contiguous block of array lines of those exiting to the one side.

7. The integrated circuit as recited in claim 1 wherein the extent of each intermediate node is at least half the distance along the one side of the sub-array.

8. The integrated circuit as recited in claim 3 wherein each of the plurality of second-level signals selects a respective group of at least one of the plurality of intermediate nodes and, when unselected, couples its respective intermediate node to an associated unselected bias node, thereby coupling array lines that are coupled to the respective intermediate node a selected top-level signal, to the associated unselected bias node.

9. The integrated circuit as recited in claim 1 wherein the plurality of array lines on at least one layer of the memory sub-array includes array lines which exit to the side opposite the one side of the memory array.

10. The integrated circuit as recited in claim 1 wherein each selected intermediate node is coupled to an associated sense amplifier input node.

17. The integrated circuit as recited in claim 1 wherein each of the first plurality of selection circuits is configured to couple, when unselected, its associated array line to an associated unselected bias node.

18. The integrated circuit as recited in claim 17 further comprising at least one unselected array line bias circuit for respectively generating an unselected bias voltage on at least one unselected bias node.

19. The integrated circuit as recited in claim 17 wherein each of the second plurality of selection circuits is configured to couple, when unselected, its respective intermediate node to an associated unselected bias node, thereby coupling array lines that are coupled to the respective intermediate node by selected array line coupling circuits, to the associated unselected bias node.

11. An integrated circuit comprising:

a memory sub-array comprising a plurality of array lines on at least one layer of the memory sub-array having at least some of the array lines exiting to one side of the memory sub-array;

a tree decoder circuit associated with the memory sub-array, said tree decoder comprising

a first plurality of selection circuits, each responsive to an associated one of a first plurality of decode signals, for coupling, when selected, a respective array line to an associated one of a plurality of intermediate nodes of the tree decoder, said intermediate nodes each having a respective extent along the one side of the sub-array;

a second plurality of selection circuits, each responsive to an associated one of a second plurality of decode signals, for coupling, when selected, a respective intermediate node to an associated other node of the tree decoder;

wherein each of the first plurality of decode signals has a range of control that extends a distance along the one side of the sub-array which is substantially less than the extent of the intermediate nodes.

12. The integrated circuit as recited in claim 11 wherein the memory sub-array comprises a three-dimensional memory sub-array comprising at least two layers of array lines having at least some array lines exiting to the one side of the memory sub-array.

13. The integrated circuit as recited in claim 12 wherein each respective one of the first plurality of decode signals selects a respective group of at least two array lines on each of at least two layers of the memory sub-array.

14. The integrated circuit as recited in claim 13 wherein each of the first plurality of selection circuits is configured to couple, when unselected, its associated array line to an associated unselected bias node for the respective sub-array layer.

15. The integrated circuit as recited in claim 13 wherein each respective group comprises a contiguous block of array lines of those exiting to the one side.

16. The integrated circuit as recited in claim 15 wherein said contiguous block comprises at least two adjacent array lines of those exiting the one side of the memory sub-array on each of at least two layers.

20. The integrated circuit as recited in claim 11 wherein the plurality of array lines on at least one layer of the memory sub-array includes array lines which exit to the side opposite the one side of the memory array.

21. The integrated circuit as recited in claim 11 wherein each intermediate node coupling circuit is configured to couple, when selected, its respective intermediate node to an associated sense amplifier input node.

22. The integrated circuit as recited in claim 11 wherein:

the memory sub-array is disposed above a semiconductor substrate of the integrated circuit; and

each of the first plurality of decode signals is generated by a decoder circuit disposed at least partially beneath the memory array.

23. An integrated circuit comprising:

a memory sub-array having a plurality of array lines on at least one layer of the memory sub-array, at least some of the array lines exiting to one side of the memory sub-array;

a first decoder circuit responsive at least to address signals, for generating a first plurality of decode signals, and for generating a second plurality of decode signals;

a first plurality of array line coupling circuits, each responsive to an associated one of the first plurality of decode signals, for coupling, when selected, a respective array line to an associated one of a plurality of intermediate nodes, said intermediate nodes each having a respective extent along the one side of the sub-array;

a first plurality of intermediate node coupling circuits, each responsive to an associated one of the second plurality of decode signals, for coupling, when selected, a respective intermediate node to an associated other node;

wherein each of the first plurality of decode signals is associated with a respective group of the array line coupling circuits, each respective array line coupling circuit within a given group for coupling, when selected, a respective array line to a respective intermediate node;

wherein each of the first plurality of decode signals has a range of control that extends a distance along the one side of the sub-array which is substantially less than the extent of the intermediate nodes.

24. The integrated circuit as recited in claim 23 wherein the memory sub-array comprises a three-dimensional memory sub-array comprising at least two layers of array lines having at least some array lines exiting to the one side of the memory sub-array.

25. The integrated circuit as recited in claim 24 wherein each respective group of array lines associated with a respective one of the first plurality of decode signals includes at least two array lines on each of at least two layers of the memory sub-array.

26. The integrated circuit as recited in claim 25 wherein each array line coupling circuit is configured to couple, when unselected, its associated array line to an associated unselected bias node for the respective sub-array layer.

27. The integrated circuit as recited in claim 26 further comprising a plurality of unselected array line bias circuits, each associated with a respective layer of the memory array, each for generating a respective unselected bias voltage on a respective unselected bias node for the respective sub-array layer.

28. The integrated circuit as recited in claim 25 wherein each respective group comprises a contiguous block of array lines of those exiting to the one side.

29. The integrated circuit as recited in claim 23 wherein the extent of each intermediate node is at least half the distance along the one side of the sub-array.

30. The integrated circuit as recited in claim 23 wherein each array line coupling circuit is configured to couple, when unselected, its respective array line to an associated unselected bias node.

31. The integrated circuit as recited in claim 30 further comprising at least one unselected array line bias circuit for respectively generating an unselected bias voltage on at least one unselected bias node.

32. The integrated circuit as recited in claim 30 wherein each intermediate node coupling circuit is configured to couple, when unselected, its respective intermediate node to an associated unselected bias node, thereby coupling array lines that are coupled to the respective intermediate node by selected array line coupling circuits, to the associated unselected bias node.

33. The integrated circuit as recited in claim 23 wherein the plurality of array lines on at least one layer of the memory sub-array includes array lines which exit to the side opposite the one side of the memory array.

34. The integrated circuit as recited in claim 23 wherein each intermediate node coupling circuit is configured to couple, when selected, its respective intermediate node to an associated sense amplifier input node.

35. The integrated circuit as recited in claim 30 wherein each of the plurality of array line coupling circuits comprises:

a first transistor device for coupling the respective array line to the associated intermediate node; and

a second transistor device for coupling the respective array line to the associated unselected bias node.

36. The integrated circuit as recited in claim 35 wherein each of the plurality of intermediate node coupling circuits comprises:

a first transistor device for coupling the respective intermediate node to an associated decoder output node; and

a second transistor device for coupling the respective intermediate node to the associated unselected bias node, thereby coupling array lines coupled thereto by selected array line coupling circuits, to the associated unselected bias node.

37. The integrated circuit as recited in claim 23 wherein:

each of the first plurality of decode nodes is routed into the first plurality of array line coupling circuits from a side thereof opposite the memory sub-array.

38. The integrated circuit as recited in claim 23 wherein:

the memory sub-array is disposed above a semiconductor substrate of the integrated circuit; and

the first decoder circuit is disposed in the semiconductor substrate at least partially beneath the memory sub-array.

39. An integrated circuit comprising:

a three-dimensional memory array having a respective plurality of array lines for at least two respective memory array layers exiting to one side of the memory array;

means for simultaneously coupling, in response to a single selected decode node, at least two array lines exiting to the one side of the memory array, on each of at least two memory array layers, to respective intermediate nodes.

40. The integrated circuit as recited in claim 39 wherein the means for simultaneously coupling comprises:

means for simultaneously coupling, in response to a single decode node when unselected, at least two adjacent array lines exiting to the one side of the memory array, on each of at least two memory array layers, to a respective unselected bias potential for the respective layer.

41. The integrated circuit as recited in claim 39 wherein the means for simultaneously coupling comprises:

a plurality of multi-headed decoder circuits, each comprising a respective plurality of array line coupling circuits responsive to a respective one of a plurality of decode nodes.