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Apparatus and method for controlling priority order of access to memory

  • US 6,859,614 B1
  • Filed: 06/24/1997
  • Issued: 02/22/2005
  • Est. Priority Date: 06/24/1996
  • Status: Expired due to Term
First Claim
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1. An apparatus having a memory controller for controlling access to a memory by a plurality of devices, the apparatus comprising:

  • a priority order controller to generate either an acknowledgement signal to a corresponding one of the plurality of devices in response to a request signal generated by the corresponding device, or the acknowledgement signal to the corresponding device according to a predetermined priority order if more than one request signal is simultaneously generated from the plurality of devices, and to subsequently deactivate the generated acknowledgement signal if an access actuation signal is deactivated, wherein the access actuation signal is distinct from the request signal and is issued by the memory controller to indicate that one of the plurality of devices is accessing the memory.

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