Apparatus and method for controlling priority order of access to memory

• US 6,859,614 B1
• Filed: 06/24/1997
• Issued: 02/22/2005
• Est. Priority Date: 06/24/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Chan-Dong
• Primary Examiner(s): Tran, Thai
• Assistant Examiner(s): ONUAKU, CHRISTOPHER O
• Application Number:
  US08/881,123
• Time in Patent Office: 2,800 Days
• Field of Search: 386/45, 386/46, 386/125, 386/126, 386/124, 348/7, 348/10, 348/13, 348/12, 711/151, 711/158, 711/106, 725/111, 725/121, 725/131
• US Class Current: 386/231
• CPC Class Codes: H04N 21/42646 for reading from or writing on a non-volatile solid state storage medium, e.g. DVD, CD-ROM
• CPC Class Codes: H04N 21/4435 Memory management allocation of memory to service a request G06F9/5016; addressing or allocating within memory systems or architectures G06F12/02
• CPC Class Codes: H04N 5/85 on discs or drums

Abstract

An apparatus for controlling an access to a memory in a system decoder of a digital video disk player. The digital video disk player includes several devices which access the memory. A memory controller connected to the devices and a data/address bus controls access to the memory. A priority order controller allows the devices to access the memory according to a predetermined priority order. The priority order controller generates acknowledgement signals to the corresponding devices in response to request signals generated from the devices. If two or more request signals are simultaneously generated from the devices, the priority order controller generates an acknowledgement signal to the appropriate device according to a predetermined priority order of the devices. Further, the acknowledgement signal is deactivated, if an access actuation signal is deactivated.

Claims

1. An apparatus having a memory controller for controlling access to a memory by a plurality of devices, the apparatus comprising:

a priority order controller

to generate either

an acknowledgement signal to a corresponding one of the plurality of devices in response to a request signal generated by the corresponding device, or

the acknowledgement signal to the corresponding device according to a predetermined priority order if more than one request signal is simultaneously generated from the plurality of devices, and

to subsequently deactivate the generated acknowledgement signal if an access actuation signal is deactivated,

wherein the access actuation signal is distinct from the request signal and is issued by the memory controller to indicate that one of the plurality of devices is accessing the memory.

2. The apparatus of claim 1, wherein said priority order controller, when the access actuation signal is no longer being issued, further transmits a next acknowledgement signal relating to another request signal that both correspond to another one of the devices and was generated while the access activation signal was issued.

3. An apparatus for controlling access to a memory comprising:

a plurality of devices which access the memory, each of said plurality of devices generating a corresponding request signal to request access to the memory and forming a communication path to a data/address bus in response to a corresponding acknowledgement signal;

a memory controller, connected between the memory and said plurality of devices, to control communication between the memory and said plurality of devices in response to an access request signal, said memory controller to generate an access actuation signal during access by one of said plurality of devices; and

a priority order controller

to generate acknowledgement signals to corresponding ones of the devices in response to request signals from the corresponding ones of the devices,

to generate the acknowledgement signal to the corresponding one of the devices according to a predetermined priority order of the devices if greater than one request signal is simultaneously generated by said plurality of devices,

to generate and transmit the access request signal to said memory controller in response to the generation of the corresponding acknowledgement signal, and

if the request signal is generated during generation of the access actuation signal, to transmit a next acknowledgement signal relating to the request signal generated during generation of the access actuation signal to a corresponding one of the devices when the access actuation signal is no longer being generated,

where the access actuation signal is distinct from the request signal.

4. A digital video disk apparatus comprising:

a microcomputer to control the apparatus;

a memory to store data;

a disk revolution controller to rotate a digital video disk according to a control signal of said microcomputer;

a data/address bus;

a demodulator connected to said data/address bus for demodulating data read from the digital video disk, said demodulator to generate a second request signal for requesting access to said memory and forming a communication path with said memory in response to a second acknowledgement signal;

an error correction circuit connected to said data/address bus for correcting errors in the demodulated data output from said demodulator, said error correction circuit to generate a first request signal for requesting access to said memory and to form a communication path with said memory in response to a first acknowledgement signal;

a descrambler connected to said data/address bus to descramble the error corrected data output from said error correction circuit, said descrambler to generate a third request signal for requesting access to said memory and to form a communication path with said memory in response to a third acknowledgement signal;

a microcomputer memory access controller connected to said data/address bus for allowing said microcomputer to access said memory, said microcomputer memory access controller to generate a fourth request signal for requesting access to said memory and to form a communication path with said memory in response to a fourth acknowledgement signal;

an interface connected to said data/address bus to transfer the descrambled data output from said descrambler to at least one of an audio/video decoder and a host in response to a control signal from said microcomputer, said interface to generate a fifth request signal for requesting access to said memory and to form a communication path to said memory in response to a fifth acknowledgement signal;

a memory refresh circuit connected to said data/address bus to refresh said memory, said memory refresh circuit to generate a sixth request signal for requesting access to said memory and forming a communication path to said memory in response to a sixth acknowledgement signal;

a memory controller connected between said memory and said data/address bus, to control communication with said memory via the data/address bus in response to an access request signal, and generating an access actuation signal during access of said memory; and

a priority order controller to generate the first to sixth acknowledgement signals in accordance with a sequence of the first to sixth request signals, said priority order controller to generate the first to sixth acknowledgement signals according to a predetermined priority order if more than one of the first to sixth request signals are simultaneously generated, said priority order controller to generate the access request signal while generating each of the first to sixth acknowledgement signals, wherein the one of the first through sixth request signal received during generation of the access actuation signal is maintained in a stand-by state and the acknowledgement signal corresponding to the one request signal received during generation of the access actuation signal is generated after completion of the access actuation signal.

5. The digital video disk apparatus according to claim 4, wherein the predetermined priority order is determined according to a sequence of the first to sixth request signals.

6. A method for controlling access of a plurality of devices to a memory, comprising:

generating an individual acknowledgement signal in response to a request signal from one of the devices;

generating the individual acknowledgement signal for the appropriate one of the devices according to a predetermined priority order of the devices when more than one request signal is simultaneously generated by the devices;

generating an access actuation signal that is distinct from the request signal and indicates that one of the plurality of devices is accessing the memory;

deactivating the access actuation signal after the one device has finished accessing the memory; and

deactivating the acknowledgement signal after the access actuation signal is deactivated.

7. A method for controlling access of a plurality of devices to a memory, comprising:

generating a request signal for each device which is requesting access to the memory;

generating an acknowledgement signal to one device corresponding to a request signal, the one device being selected according to a predetermined priority order;

forming a communication path between the one device and the memory via a data/address bus in response to the acknowledgement signal to allow the one device access to the memory;

generating an access actuation signal that is distinct from the request signal during access by the one device to the memory;

activating an acknowledgement signal while the access actuation sign al is activated, and deactivating the acknowledgement signal when the access actuation signal is deactivated.

8. The method of claim 7, further comprising

receiving another request signal from another device which is requesting access to the memory while the access actuation signal is activated;

and

generating a next acknowledgement signal relating to the another request signal when the access actuation signal is no longer being generated.

9. The method of claim 8, wherein said generating the next acknowledgement signal comprises generating the next acknowledgement signal according to the predetermined order of the devices if multiple requests are received while the access actuation signal was actuated.

10. An apparatus comprising:

a memory accessible by a single device at a time;

a plurality of devices which access said memory;

a memory controller that generates an access actuation signal to indicate that one of said plurality of devices is accessing said memory; and

a priority order discriminator which receives a request from each device requesting access to said memory, said priority order discriminator outputting an acknowledgement signal to one of said plurality of devices indicating that the one device may access said memory, the one device being selected based on a predetermined priority order among said plurality of devices,

wherein

the one device forms a communication path with said memory and accesses said memory when the one device receives the acknowledgement signal, and said priority order discriminator deactivates the acknowledgement signal upon the deactivation of the access actuation signal, and

the access actuation signal is distinct from the request.

11. An apparatus, according to claim 10, further comprising:

a bus connecting each of said plurality of devices to said memory; and

a plurality of communication paths connecting said priority order discriminator to each of said plurality of devices and said memory.

12. An apparatus, according to claim 11, wherein said memory comprises:

a storage area for storing data;

wherein said apparatus further comprises a memory controller connected to said storage area and said bus for allowing access to said storage area by said plurality devices, said memory controller outputting an access signal, via a communication path, to said priority order discriminator indicating that said memory is being accessed.

13. An apparatus, according to claim 12, wherein while said priority order discriminator receives the access signal from said memory controller any additional requests from the devices for access to the memory are held in a stand-by state.

14. The apparatus of claim 13, wherein said priority order discriminator further receives another request signal from another of said plurality of devices while the access actuation signal is generated, and transmits a next acknowledgement signal relating to the another request signal when the access actuation signal is deactivated.

15. An apparatus, according to claim 11, wherein said priority order discriminator selects the single device based on an order of priority of the communication path to which said device is connected.

16. An apparatus, according to claim 11, further comprising:

a logic circuit which outputs a request signal to said memory controller, via a communication path, while said priority order discriminator is outputting an acknowledgement signal to indicate to said memory that a device will be making access to said memory.

17. The apparatus of claim 10, wherein said priority order discriminator further receives another request signal from another of said plurality of devices while the access actuation signal is generated, and transmits a next acknowledgement signal relating to the another request signal when the access actuation signal is deactivated.

18. An apparatus for controlling access to a memory by a plurality of devices, the apparatus comprising:

a memory controller to issue an access actuation signal, wherein the access actuation signal is issued to indicate that one of the plurality of devices is accessing the memory; and

a priority order controller

to generate an acknowledgement signal to a corresponding one of the plurality of devices in response to a request signal generated by the corresponding device,

to generate the acknowledgement signal to the corresponding device according to a predetermined priority order if more than one of the plurality of devices simultaneously accesses the memory, and

to subsequently deactivate the generated acknowledgement signal if the access actuation signal is deactivated,

wherein the access actuation signal is distinct from the request signal.

19. An apparatus for controlling access to a memory comprising:

a plurality of devices which access the memory, each of said plurality of devices generating a corresponding request signal for requesting access to the memory and forming a communication path to a data/address bus in response to a corresponding acknowledgement signal;

a memory controller, connected between the memory and said plurality of devices, to control communication between the memory and said plurality of devices in response to an access request signal, said memory controller to generate an access actuation signal distinct from the request signal during access by one of said plurality of devices; and

a priority order controller

to generate acknowledgement signals to corresponding ones of the devices in response to request signals from the corresponding ones of the devices,

to generate the acknowledgement signal to the corresponding one of the devices according to a predetermined priority order of the devices if greater than one of said plurality of devices simultaneously requests access to the memory,

to generate and transmit the access request signal to said memory controller in response to the generation of the corresponding acknowledgement signal, and

if the request signal is generated during generation of the access actuation signal, to transmit a next acknowledgement signal relating to the request signal generated during generation of the access actuation signal to a corresponding one of the devices when the access actuation signal is no longer being generated.

20. The apparatus of claim 19, wherein said priority order controller transmits the next acknowledgement signal according to the predetermined order of the devices.