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Method and apparatus for generating transaction-based stimulus for simulation of VLSI circuits using event coverage analysis

  • US 6,859,770 B2
  • Filed: 11/30/2000
  • Issued: 02/22/2005
  • Est. Priority Date: 11/30/2000
  • Status: Expired due to Term
First Claim
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1. A method of simulating a circuit, comprising the steps of:

  • identifying a set of logic events associated with said circuit, wherein the logic events are represented as data objects embodying logic equations;

    generating a plurality of input test cases;

    simulating operation of said circuit utilizing said plurality of input test cases;

    tabulating for the plurality of input test cases and the set of logic events the numbers of times that each input test case stimulates logic event; and

    identifying as non-occurring events one or more logic events that have not been stimulated more than a predetermined threshold of times.

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