Method and apparatus for generating transaction-based stimulus for simulation of VLSI circuits using event coverage analysis

• US 6,859,770 B2
• Filed: 11/30/2000
• Issued: 02/22/2005
• Est. Priority Date: 11/30/2000
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Ramsey, Clinton M.
• Primary Examiner(s): PALADINI, ALBERT WILLIAM
• Application Number:
  US09/727,188
• Publication Number:
  US 20020065640A1
• Time in Patent Office: 1,545 Days
• Field of Search: 703/14, 703/15, 703/16, 714/739, 714/738, 702/183, 717/135
• US Class Current: 703/16
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

The present invention applies genetic algorithmic generation of test cases the simulation of VLSI logic circuit blocks. The present invention generates a number of original test cases. This aggregate of solutions is provided to a circuit simulator. The results of the simulator are maintained in a matrix or table. The results detail the number of times that particular logic states or events associated with the VLSI block have been stimulated by particular test cases. The aggregate of solutions and the simulation results are then analyzed by the genetic algorithm. The genetic algorithm preferably identifies states associated with the circuit simulation that have not been produced by the original test cases. The genetic algorithm then combines characteristics of various test cases to generate new test cases. The new test cases are provided to the circuit simulator thereby providing a higher degree of confidence that the entire VLSI chip design has been simulated.

Claims

1. A method of simulating a circuit, comprising the steps of:

identifying a set of logic events associated with said circuit, wherein the logic events are represented as data objects embodying logic equations;

generating a plurality of input test cases;

simulating operation of said circuit utilizing said plurality of input test cases;

tabulating for the plurality of input test cases and the set of logic events the numbers of times that each input test case stimulates logic event; and

identifying as non-occurring events one or more logic events that have not been stimulated more than a predetermined threshold of times.

2. The method of claim 1 further comprising the steps of:

selecting one event of said non-occurring events; and

comparing a logic equation of said one event against logic equations of logic events that have been stimulated more than a predetermined threshold.

3. The method of claim 2 wherein the step of comparing comprises the sub-step of:

assigning scores to compared events, wherein said scores reflect similarity to said one event.

4. The method of claim 3 further comprising the step of:

utilizing said scores and said numbers of times to weight instructions contained in said input test cases.

5. The method of claim 4 further comprising the step of:

constructing a new test case from said weighted instructions.

6. The method of claim 5 wherein each test case possesses a plurality of instructions with each instruction respectively associated with generation strides.

7. The method of claim 6 wherein the generation strides are relatively prime.

8. The method of claim 5 wherein the step of tabulating comprises the sub-step of:

recording numbers of times in a matrix.

9. The method of claim 7 wherein the step of construction comprises the sub-step of:

assigning heavily weighted instructions to lower strides.

10. The method of claim 7 wherein the step of construction comprises the sub-step of:

weighting strides associated with particular instructions.

11. A system for simulating, comprising:

a data structure including a set of logic events associated with said circuit, wherein the logic events are represented as data objects embodying logic equations;

a first software routine generating a plurality of input test cases;

a second software routine applying said plurality of input test cases to a circuit simulator;

a third software routine tabulating for the plurality of input test cases and the set of logic events the numbers of times that each input test case stimulates each logic event; and

a fourth software routine identifying as non-occurring events one or more logic events that have not been stimulated more than a predetermined threshold of times.

12. The system of claim 11 further comprising:

a fifth software routine selecting one event of said non-occurring events; and

a sixth software routine comparing a logic equation of said one event against logic equations of logic events that have been simulated more than a predetermined threshold.

13. The system of claim 12 wherein said sixth software routine assigns scores to compared events, wherein said scores reflect similarity to said one event.

14. The system of claim 13 further comprising:

a seventh software routine utilizing said scores and said numbers of times to weight instructions contained in said input test cases.

15. The system of claim 14 further comprising:

an eighth software routine constructing a new test case from said weighted instructions.

16. The system of claim 15 wherein each test case possesses a plurality of instructions with each instruction respectively associated with generation strides.

17. The system of claim 16 wherein the generation strides are relatively prime.

18. The system of claim 15 wherein the third software routine records numbers of times in a matrix.

19. A computer program product having a computer readable medium having programmable logic recorded thereon for testing a circuit, the computer product comprising:

means for representing a set of logic events associated with said circuit as data objects embodying logic equations;

means for generating a plurality of input test cases for application to a circuit simulator;

means for tabulating for the plurality of input test cases and the set of logic events the numbers of times that each input test case stimulates each logic event;

means for identifying as non-occurring events one or more logic events that have not been stimulated more than a predetermined threshold of times;

means for selecting one event of said non-occurring events; and

means for comparing a logic equation of said one event against logic equations of logic events that have been simulated more than a predetermined threshold.

20. A computer program product of claim 19 further comprising:

means for weighting instructions contained in said input test cases utilizing output from said means for comparing and said numbers of times; and

means for constructing a new test case from said weighted instructions.