Method and apparatus for software management of on-chip cache

• US 6,859,862 B1
• Filed: 04/07/2000
• Issued: 02/22/2005
• Est. Priority Date: 04/07/2000
• Status: Expired due to Term

• Current Assignee: Nintendo Company Limited
• Original Assignee: Nintendo Company Limited
• Inventors: Cheng, Howard, Liao, Yu-Chung C., Sandon, Peter A., Hsu, Peter
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US09/545,184
• Time in Patent Office: 1,782 Days
• Field of Search: 711/130, 711/129, 711/133, 711/170, 711/123, 711/217, 711/214, 711/215, 711/220, 711/219, 711/173, 711/163, 711/152, 711/153, 712/35, 712/36, 712/22, 712/222, 712/4
• US Class Current: 711/129
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions

Abstract

A microprocessor including a control unit and a cache connected with the control unit for storing data to be used by the control, wherein the cache is selectively configurable as either a single cache or as a partitioned cache having a locked cache portion and a normal cache portion. The normal cache portion is controlled by a hardware implemented automatic replacement process. The locked cache portion is locked so that the automatic replacement process cannot modify the contents of the locked cache. An instruction is provided in the instruction set that enables software to selectively allocate lines in the locked cache portion to correspond to locations in an external memory, thereby enabling the locked cache portion to be completely managed by software.

Claims

1. A microprocessor, comprising a control unit and a cache connected with the control unit for storing data to be used by the control unit, wherein the cache is selectively configurable as either a single cache or as a partitioned cache having a locked cache portion and a normal cache portion, the normal cache portion being controlled by a hardware implemented automatic replacement process, and further wherein the locked cache portion is locked so that the automatic replacement process cannot modify the contents of the locked cache portion,

an instruction that enables software to selectively allocate lines in the locked cache portion to correspond to locations in an external memory, and

a direct memory access engine that controls transfer of data between the locked cache portion and the external memory, wherein the direct memory access engine includes first and second special purpose registers, wherein the first special purpose register controls transfer of data from the external memory into the locked cache potion and the second special purpose register controls transfer of data from the locked cache portion to the external memory.

2. A microprocessor, comprising a control unit and a cache connected with the control unit for storing data to be used by the control unit, wherein the cache is selectively configurable as either a single cache or as a partitioned cache having a locked cache portion and a normal cache portion, the normal cache portion being controlled by a hardware implemented automatic replacement process, and further wherein the locked cache portion is locked so that the automatic replacement process cannot modify the contents of the locked cache portion, and

an instruction that enables software to selectively allocate lines in the locked cache portion to correspond to locations in an external memory,

wherein the microprocessor further includes a hardware implementation dependent special purpose register which determines whether the cache is configured as the single normal cache or the partitioned cache.