Method and circuit for allowing a microprocessor to change its operating frequency on-the-fly
First Claim
1. A circuit that allows a processor forming a part of a microcontroller to change its operating frequency, comprising:
- a clock generator generating a plurality of clock signals at a plurality of frequencies;
a first switch receiving the plurality of clock signals and selecting one of the clock signals as an output thereof to be the current clock according to a current speed select signal;
a current speed latch storing the current speed select signal;
a first phase shifter shifting the phase of the current clock to produce a phase shifted current clock;
a second switch receiving the plurality of clock signals and selecting one of the clock signals as an output thereof to be the new clock according to a new speed select signal;
a new speed register storing the new speed select signal;
wherein, the new speed select signal is produced by the processor and stored in the new speed register;
a second phase shifter shifting the phase of the new clock to produce a phase shifted new clock; and
logic means, receiving the current clock, the phase shifted current clock, the new clock, the phase shifted new clock and a signal from the processor directing a speed change as inputs thereto, the logic means for producing a signal latching the new speed into the current speed latch at a point in time after the speed change signal when the current clock, phase shifted current clock, the new clock and the phase shifted new clock have the same state.
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Accused Products
Abstract
A circuit that permits a processor in a microcontroller to adjust its clock speed on the fly. A processor receives a current clock signal and a phased current clock signal from a speed selection switch. A new speed selection switch provides a new clock signal and a phased new clock signal for comparison with the current clock signals. When the states of the current and new clocks appropriately align after issuance of a control from the processor, the new speed is switched into the current speed switch to permit the clock speed to change without producing spurious signals that cause unpredictable action in the processor. This advantageously allows the microcontroller to adjust its clock speed under program control.
89 Citations
20 Claims
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1. A circuit that allows a processor forming a part of a microcontroller to change its operating frequency, comprising:
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a clock generator generating a plurality of clock signals at a plurality of frequencies;
a first switch receiving the plurality of clock signals and selecting one of the clock signals as an output thereof to be the current clock according to a current speed select signal;
a current speed latch storing the current speed select signal;
a first phase shifter shifting the phase of the current clock to produce a phase shifted current clock;
a second switch receiving the plurality of clock signals and selecting one of the clock signals as an output thereof to be the new clock according to a new speed select signal;
a new speed register storing the new speed select signal;
wherein, the new speed select signal is produced by the processor and stored in the new speed register;
a second phase shifter shifting the phase of the new clock to produce a phase shifted new clock; and
logic means, receiving the current clock, the phase shifted current clock, the new clock, the phase shifted new clock and a signal from the processor directing a speed change as inputs thereto, the logic means for producing a signal latching the new speed into the current speed latch at a point in time after the speed change signal when the current clock, phase shifted current clock, the new clock and the phase shifted new clock have the same state. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A circuit that allows a processor forming a part of a microcontroller to change its operating frequency, comprising:
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a clock generator generating a plurality of clock signals at a plurality of frequencies;
a first switch receiving the plurality of clock signals and selecting one of the clock signals as an output thereof to be the current clock according to a current speed select signal;
a current speed latch storing the current speed select signal;
a first phase shifter shifting the phase of the current clock to produce a phase shifted current clock;
a second switch receiving the plurality of clock signals and selecting one of the clock signals as an output thereof to be the new clock according to a new speed select signal;
a new speed register storing the new speed select signal;
wherein, the new speed select signal is produced by the processor and stored in the new speed register;
a second phase shifter shifting the phase of the new clock to produce a phase shifted new clock;
logic means, receiving the current clock, the phase shifted current clock, the new clock, the phase shifted new clock and a signal from the processor directing a speed change as inputs thereto; and
the logic means producing a latching signal latching the new speed into the current speed latch at a point in time after the speed change signal when the current clock has the same state as the new clock, and when the phase shifted current clock has the same state as the phase shifted new clock. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A circuit that allows a processor forming a part of a microcontroller to change its operating frequency, comprising:
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a master clock generating a master clock signal;
a clock generator generating a plurality of clock signals from the master clock signal at a plurality of frequencies by dividing the master clock signal using a plurality of series connected flip flops;
a first switch receiving the plurality of clock signals and selecting one of the clock signals as an output thereof to be the current clock according to a current speed select signal;
a current speed latch storing the current speed select signal, a first phase shifter shifting the phase of the current clock to produce a phase shifted current clock by delaying the current clock by a fixed delay;
a second switch receiving the plurality of clock signals and selecting one of the clock signals as an output thereof to be the new clock according to a new speed select signal;
a new speed register storing the new speed select signal;
wherein, the new speed select signal is produced by the processor and stored in the new speed register;
a second phase shifter shifting the phase of the new clock to produce a phase shifted new clock by delaying the new clock by a fixed delay; and
a logic NOR gate, receiving as inputs the current clock, the phase shifted current clock, the new clock, the phase shifted new clock and a signal from the processor directing a speed change as inputs thereto, the NOR gate producing a signal latching the new speed into the current speed latch at a point in time when speed change signal, the current clock, phase shifted current clock, the new clock and, the phase shifted new clock have the same state. - View Dependent Claims (15)
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16. A method for a processor forming a part of a microcontroller to change its clock frequency, comprising:
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at the processor, receiving a clock signal;
determining that the clock frequency is to be changed under program control;
storing a new clock frequency signal in a new speed register;
issuing an I/O write command indicating that the clock frequency is to change;
in a logic circuit, examining a current clock signal, a new clock signal, a phase shifted current clock signal and a phase shifted new clock signal;
when the current clock signal, the new clock signal, the phase shifted current clock signal and the phase shifted new clock signal reach predetermined states, latching the new clock frequency signal into a current clock speed latch; and
at a switch, receiving an output from the current clock speed latch and changing a switch setting in response thereto, the switch setting determining the speed of the clock signal. - View Dependent Claims (17, 18, 19, 20)
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Specification