Method for creating thick oxide on the bottom surface of a trench structure in silicon

• US 6,861,296 B2
• Filed: 06/19/2002
• Issued: 03/01/2005
• Est. Priority Date: 08/16/2000
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Hurst, Henry W., Murphy, James J.
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Toledo, Fernando L.
• Application Number:
  US10/177,783
• Publication Number:
  US 20020153557A1
• Time in Patent Office: 986 Days
• Field of Search: 438/138, 438/268, 438/270, 438/424, 438/430, 438/981, 438/FOR.176, 438/FOR.192
• US Class Current: 438/138
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A gate isolation structure of a semiconductor device and method of making the same provides a trench in a silicon substrate, wherein a dielectric layer is formed on sidewalls and bottom of the trench, the dielectric layer having a first thickness on the sidewalls and a second thickness at the bottom that is greater than the first thickness. The thicker dielectric layer at the bottom substantially reduces gate charge to reduce the Miller Capacitance effect, thereby increasing the efficiency of the semiconductor device and prolonging its life.

Claims

1. A method of forming a gate dielectric layer of a trenched gate field effect transistor having source regions proximate the trenched gate, the method comprising the steps of:

forming a trench extending into a silicon region;

forming a first layer of a dielectric material extending at least along sidewalls and bottom of the trench; and

forming a second layer of dielectric material at the bottom of the trench such that a thickness of the first layer of a dielectric material smoothly changes from a substantially uniform thickness along the sidewalls of the trench to a thickness of the combined first and second layers of dielectric material along the bottom of the trench without a reduction in thickness in the transition region from the trench sidewalls to the trench bottom.

2. The method according to claim 1 further comprising the steps of:

forming a layer of oxidation-inhibiting material on the first layer of dielectric material; and

removing a portion qf the oxidation-inhibiting material from the bottom of the trench.

3. The method according to claim 1 wherein the dielectric material is silicon dioxide.

4. The method according to claim 2 further comprising the step of removing remaining portions of the oxidation-inhibiting material.

5. The method according to claim 2 wherein the oxidation-inhibiting material is silicon nitride.

6. The method according to claim 1, further comprising the step of masking the silicon region proximate the trench with a hard mask.

7. The method of according to claim 6, further comprising the steps of:

forming a layer of oxidation-inhibiting material over the first layer of dielectric material and the hard mask; and

etching portions of the oxidation-inhibiting material from the bottom of the trench.

8. The method according to claim 7 wherein the oxidation-inhibiting material is silicon nitride.

9. The method of claim 1 wherein the first layer of dielectric material comprises a conformal layer of silicon dioxide.

10. The method of claim 1 wherein the first layer of dielectric material comprises a pad oxide having a thickness in the range of 200-1000 Å

.

11. The method of claim 2 wherein the layer of oxidation-inhibiting material is formed using plasma enhanced chemical vapor deposition.

12. The method of claim 2 wherein the layer of oxidation-inhibiting material has a non-uniform thickness.

13. The method of claim 2 wherein the layer of oxidation-inhibiting material has a greater thickness along the trench bottom than along the trench sidewalls.

14. The method of claim 2 wherein the layer of oxidation-inhibiting material further extends over the silicon region proximate the trench, and the portion of the layer of oxidation-inhibiting material extending over the silicon region proximate the trench has a greater thickness than the portion of the layer of oxidation-inhibiting material at the trench bottom.

15. The method of claim 2 wherein the removing step is carried out using directional anisotropic etchback.

16. The method of claim 2 wherein the second layer of dielectric material is formed by local oxidation of the portion of the silicon region along the trench bottom.

17. The method of claim 1 wherein the first layer of dielectric material further extends over the silicon region surface proximate the trench, the method comprising:

forming a layer of oxidation-inhibiting material on the first layer of dielectric material; and

removing a portion of the oxidation-inhibiting material from the bottom of the trench such that portions of the layer of oxidation-inhibiting material extending along the trench sidewalls and over the silicon region surface proximate the trench remain.

18. The method of claim 17 wherein the removing step is carried out using directional anisotropic etchback.

19. The method of claim 1 further comprising the steps of:

forming a layer of oxidation-inhibiting material on the first layer of dielectric material; and

removing the oxidation-inhibiting material to expose portions of the silicon region along the trench bottom and along a lower portion of the trench sidewalls.

20. The method of claim 19 wherein the second layer of dielectric material is formed by local oxidation of the exposed portions of the silicon region along the trench bottom and along the lower portion of the trench sidewalls.

21. The method of claim 7 wherein the layer of oxidation-inhibiting material has a non-uniform thickness.

22. The method of claim 7 wherein the layer of oxidation-inhibiting material has a uniform thickness.

23. The method of claim 7 wherein the layer of oxidation-inhibiting material is formed using one of plasma enhanced chemical vapor deposition and low pressure chemical vapor deposition.