JFET structure for integrated circuit and fabrication method
First Claim
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1. A method of fabricating a Junction Field Effect Transistor comprising:
- introducing at least one threshold voltage implant at an implant location associated with at least one of a gate region, a source region and a drain region;
forming the source and drain regions with one of a p-type and n-type dopant; and
forming the gate region between the source and drain regions to have one of a n-type or p-type dopant that is a different type of dopant from that used to form the source and drain regions, whereby the at least one threshold voltage implant mitigates noise associated with operation of the JFET.
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Abstract
Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.
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25 Claims
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1. A method of fabricating a Junction Field Effect Transistor comprising:
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introducing at least one threshold voltage implant at an implant location associated with at least one of a gate region, a source region and a drain region;
forming the source and drain regions with one of a p-type and n-type dopant; and
forming the gate region between the source and drain regions to have one of a n-type or p-type dopant that is a different type of dopant from that used to form the source and drain regions, whereby the at least one threshold voltage implant mitigates noise associated with operation of the JFET. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of fabricating a Junction Field Effect Transistor (JFET) in a Complementary Metal Oxide Semiconductor (CMOS) or Bipolar CMOS (BiCMOS) process, the method comprising the steps of:
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concurrently forming an epitaxial layer that defines a channel region of the JFET and associated regions of at least one of a bipolar transistor and a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the epitaxial layer having a thickness sufficient to provide the JFET with a breakdown voltage that is greater than about 20 volts;
concurrently forming source and drain regions of the JFET with source and drain regions of a corresponding first type of MOSFET; and
concurrently forming at least one gate region of the JFET with source and drain regions of a corresponding second type of MOSFET, which is different from the first type of MOSFET. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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