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Method of fabricating trench isolation structures for integrated circuits using atomic layer deposition

  • US 6,861,334 B2
  • Filed: 06/21/2001
  • Issued: 03/01/2005
  • Est. Priority Date: 06/21/2001
  • Status: Expired due to Term
First Claim
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1. A method of fabricating trench isolation structures between integrated electrical devices in a semiconductor substrate, comprising:

  • placing a semiconductor substrate in a reaction chamber, the semiconductor substrate comprising trenches; and

    completely filling the trenches with insulating material by atomic layer deposition to form a trench isolation structure, the atomic layer deposition process comprising a plurality of primary cycles, each primary cycle comprising, in sequence;

    introducing a first vapor-phase reactant to the substrate, thereby forming no more than about one monolayer of a first reactant species conforming at least to surfaces of the trenches;

    removing excess first vapor-phase reactant and byproduct from the reaction chamber;

    introducing a second vapor-phase reactant to the substrate, thereby reacting with the first reactant species conforming at least to the surfaces of the trenches; and

    removing excess second vapor-phase reactant and byproduct from the reaction chamber filling the trenches further comprises a plurality of secondary cycles, each secondary cycle comprising, in sequence;

    introducing a third vapor-phase reactant to the substrate, thereby forming no more than about one monolayer of a third reactant species conforming at least to surfaces of the trenches, the third reactant species being different from the first reactant species;

    removing excess third vapor-phase reactant and byproduct from the reaction chamber;

    introducing a fourth vapor-phase reactant to the substrate, thereby reacting with the third reactant species conforming at least to the surfaces of the trenches; and

    removing excess fourth vapor-phase reactant and byproduct from the reaction chamber wherein the primary cycles deposit a first oxide species and the secondary cycles deposit a second oxide species, wherein the primary and secondary cycles are mixed in a ratio to match a coefficient of thermal expansion (CTE) of the insulating material to within about 20% of a CTE of the semiconductor substrate.

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