Memory device with sense amplifier and self-timed latch
DCFirst Claim
1. A memory device, comprising:
- a plurality of memory cells, each of the plurality of memory cells coupled to a bit line;
a sense amplifier for amplifying a data signal from a selected one of the plurality of memory cells via the bit line to provide an amplified data signal in response to asserting a sense enable signal;
an isolation circuit, coupled between the bit line and the sense amplifier, the isolation circuit for decoupling the selected one of the plurality of memory cells from the sense amplifier at about the same time as the assertion of the sense enable signal; and
a self-timed storage device, coupled to the sense amplifier, for storing data corresponding to the amplified data signal only in response to the amplified data signal.
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Accused Products
Abstract
A memory device (201) includes a plurality of memory cells (203), bit lines, word lines, a sense amplifier (314), and a self-timed latch (215). The sense amplifier (314), responsive to a sense enable signal, is for sensing and amplifying a voltage on the bit lines corresponding to a stored logic state of a selected one of the plurality of memory cells. An isolation circuit (306, 308) is coupled between the bit lines (205 and 207) and the sense amplifier (314). The isolation circuit (306, 308) is for decoupling the selected one of the plurality of memory cells from the sense amplifier (314) at about the same time that the sense enable signal is asserted. A self-timed latch (215) is coupled to the sense amplifier (314). The self-timed latch (215) does not receive a clock signal and is responsive to only the amplified voltage.
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Citations
32 Claims
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1. A memory device, comprising:
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a plurality of memory cells, each of the plurality of memory cells coupled to a bit line;
a sense amplifier for amplifying a data signal from a selected one of the plurality of memory cells via the bit line to provide an amplified data signal in response to asserting a sense enable signal;
an isolation circuit, coupled between the bit line and the sense amplifier, the isolation circuit for decoupling the selected one of the plurality of memory cells from the sense amplifier at about the same time as the assertion of the sense enable signal; and
a self-timed storage device, coupled to the sense amplifier, for storing data corresponding to the amplified data signal only in response to the amplified data signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A memory device comprising:
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a plurality of memory cells, each of the plurality of memory cells coupled to a first bit line and to a second bit line;
a first data line coupled to the first bit line during at least a portion of a read cycle;
a second data line coupled to the second bit line during at least a portion of the read cycle;
a sense amplifier having a pair of cross-coupled inverters, the pair of cross-coupled inverters being coupled to the first data line and to the second data line for amplifying a data signal from a selected one of the plurality of memory cells in response to asserting a sense enable signal;
a first buffer circuit having an input coupled to the first data line and an output;
a second buffer circuit having an input coupled to the second data line and an output;
a self-timed storage device having a first input coupled to the output of the first buffer circuit and a second input coupled to the output of the second buffer circuit, the self-timed storage device responsive only to a differential voltage between the output of the first buffer circuit and the output of the second buffer circuit. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A method for reading a memory cell of a memory device, the memory device comprising a plurality of memory cells, each of the plurality of memory cells coupled to a bit line and to a word line, the method comprising:
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selecting at least one of the plurality of memory cells;
sensing and amplifying a voltage on the bit line using a sense amplifier in response to asserting a sense enable signal to produce an amplified data signal, the amplified data signal representative of a logic state stored in the at least one of the plurality of memory cells selected by the selecting;
decoupling the bit line from the sense amplifier at about the same time as the sense enable signal is asserted; and
latching data corresponding to the amplified data signal in a self-timed latch, the self-timed latch latching the data in response to only the amplified data signal. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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29. A method for reading a memory cell of a memory device, the memory device comprising a plurality of memory cells, the method comprising:
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selecting at least one of the plurality of memory cells;
sensing and amplifying a voltage using a sense amplifier in response to asserting a sense enable signal to produce an amplified data signal on a line, the amplified data signal representative of a logic state stored in the at least one of the plurality of memory cells selected by the selecting;
latching data corresponding to the amplified data signal in a self-timed latch, the self-timed latch latching the data in response to only the amplified data signal;
precharging the line after the sensing and amplifying, wherein the data remains latched at least during an initial portion of the precharging. - View Dependent Claims (30, 31, 32)
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Specification