Variable refresh control for a memory
First Claim
1. A memory comprising:
- a plurality of memory cells that require periodic refreshing to maintain stored data;
a variable refresh control circuit comprising a plurality of test memory cells, each of the plurality of test memory cells including a capacitor for storing charge representative of a stored logic state, the plurality of test memory cells being refreshed at a predetermined refresh rate, and each of the plurality of test memory cells being implemented to store a different amount of charge than other test memory cells of the plurality of test memory cells; and
a monitor circuit for monitoring the stored logic state of each of the plurality of test memory cells, and in response, adjusting a refresh rate of the plurality of memory cells.
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Accused Products
Abstract
A memory (10) includes a variable refresh control circuit (20) for controlling the refresh rate of a memory array (12) using a capacitor for data storage. In one embodiment, each test cell of a plurality of test memory cells (30, 32, 34, and 36) is refreshed at different rates. A monitor circuit (18) is provided for monitoring the stored logic state of each of the plurality of test memory cells, and in response, adjusting the refresh rate of the memory array (12). In another embodiment, a variable refresh control circuit (20′) includes a plurality of test memory cells (70, 72, 74, and 76) that are all refreshed at the same rate but each of the test memory cells (70, 72, 74, and 76) is implemented to have a different charge storage capacity than the other test memory cells. The monitor circuit (18) monitors the stored logic state of each of the plurality of test memory cells (70, 72, 74, and 76), and in response, adjusts a refresh rate of the memory array (12).
98 Citations
10 Claims
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1. A memory comprising:
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a plurality of memory cells that require periodic refreshing to maintain stored data;
a variable refresh control circuit comprising a plurality of test memory cells, each of the plurality of test memory cells including a capacitor for storing charge representative of a stored logic state, the plurality of test memory cells being refreshed at a predetermined refresh rate, and each of the plurality of test memory cells being implemented to store a different amount of charge than other test memory cells of the plurality of test memory cells; and
a monitor circuit for monitoring the stored logic state of each of the plurality of test memory cells, and in response, adjusting a refresh rate of the plurality of memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for refreshing a memory array having a plurality of
memory cells for storing data, comprising the steps of: -
providing a plurality of test memory cells, each of the plurality of test memory cells being implemented to have different charge storage ability than other test memory cells of the plurality of test memory cells;
refreshing the test memory cells at a predetermined refresh rate;
monitoring the charge storage ability of the plurality of test memory cells; and
adjusting the refresh rate of the memory array in response to the monitoring of the charge storage ability of the plurality of test memory cells. - View Dependent Claims (10)
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Specification