Receive deserializer circuit for framing parallel data

• US 6,862,296 B1
• Filed: 12/21/1999
• Issued: 03/01/2005
• Est. Priority Date: 12/21/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Desai, Chintan
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): ODLAND, DAVID E
• Application Number:
  US09/468,746
• Time in Patent Office: 1,897 Days
• Field of Search: 370/366, 370/503, 370/505, 370/506, 370/507, 370/509, 370/512, 370/514, 370516-518, 370/520, 375/371, 341/100, 710/30, 710/71
• US Class Current: 370/503
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15

Abstract

A receive deserializer circuit which frames parallel data utilizes a skip-bit technique for aligning a predefined data reference pattern with a word clock. The receive deserializer circuit includes a sampling flip flop which receives serial data including a data reference pattern. The sampling flip flop samples and retimes the serial data to a recovered clock. A demultiplexer then deserializes the retimed serial data into a parallel data word which is timed to a word clock from a clock generator. A comparator makes comparisons of the parallel data word with a preset data reference pattern until a match results. A logic controller interprets whether the output of the comparator is a match and generates a shift pulse following each comparison which does not result in a match. The clock generator divides the recovered clock into eight phase clocks. One of the phase clocks is a word clock. Each time the clock generator receives a shift pulse from the logic controller, it disables all the phase clocks by one bit period. This results in a one is bit shift in all the clocks and a one bit shift in the parallel data generated on word clock each time there is no match from the comparator. When a match occurs, no shift pulse is generated by the logic controller, and the predefined data reference pattern and subsequent data words received on word clock are properly framed.

Claims

1. A receive deserializer circuit which frames data, comprising:

a sampling flip flop for receiving serial data including a data reference pattern, wherein said sampling flip flop retimes said serial data to a recovered clock as sampled serial data;

a demultiplexer for deserializing said sampled serial data into a parallel data word timed to a word clock from a clock generator;

a comparator for making a comparison of said parallel data word with a preset data reference pattern until said comparison results in a match;

a logic controller for interpreting whether the output of said comparator results in said match and for generating a shift pulse following each of said comparisons which do not result in said match; and

said clock generator for dividing said recovered clock into phase clocks, said word clock being one of said phase clocks, and for disabling said phase clocks for a period of one bit upon receipt of said shift pulse, thereby creating a one bit shift in the alignment of said parallel data word being generated on said word clock by said demultiplexer.

2. The circuit as recited in claim 1, wherein said recovered clock is a local clock whose negative edge is pre-aligned with the transition edge of said serial data by a clock recovery module.

3. The circuit as recited in claim 1, wherein said recovered clock is the source clock for said phase clocks.

4. The circuit as recited in claim 1, wherein said preset data reference pattern is derived from a plurality of hard-wired connections.

5. The circuit as recited in claim 1, wherein said preset data reference pattern is derived from data received from a transmitter upon initialization of said circuit.

6. The circuit as recited in claim 1, wherein said comparator is a plurality of comparators whose outputs are combined by said logic controller to determine whether said comparator results in said match.

7. The circuit as recited in claim 6, wherein each of said plurality of comparators has a first and second input, said first input driven by a separate reference bit from said preset data reference pattern and said second input driven by a separate sample bit from said parallel data word.

8. The circuit as recited in claim 6, wherein said plurality of comparators is selected from the group consisting of operational amplifiers, logic gates and combinations thereof.

9. The circuit as recited in claim 6, wherein said plurality of comparators is eight exclusive OR logic gates.

10. A method for framing data in a receive deserializer circuit, comprising:

receiving serial data including a data reference pattern from a transmitter;

retiming said serial data to a recovered clock as sampled serial data;

deserializing said sampled serial data into a parallel data word timed to a word clock;

comparing said parallel data word with a preset data reference pattern until a match results;

generating a shift pulse when said comparing does not result in said match;

dividing said recovered clock into phase clocks, including said word clock; and

disabling said phase clocks for one bit period each time said shift pulse is generated, thereby creating a one bit shift in the alignment of said parallel data word being generated on said word clock in a demultiplexer.

11. The method as recited in claim 10, wherein said recovered clock is a local clock whose negative edge is pre-aligned with the transition edge of said serial data by a clack recovery module.

12. The method as recited in claim 10, wherein said recovered clock is the source clock for said phase clocks.

13. The method as recited in claim 10, wherein said preset data reference pattern is derived from a plurality of hard-wired connections.

14. The method as recited in claim 10, wherein said preset data reference pattern is derived from data received from a transmitter upon initialization of said receive deserializer circuit.

15. The method as recited in claim 10, wherein said comparator is a plurality of comparators whose outputs are combined by said logic controller to determine whether said camparator results in said match.

16. The method as recited in claim 15, wherein each of said plurality of comparators has a first and second input, said first input driven by a separate reference bit from said preset data reference pattern and said second input driven by a separate sample bit from said parallel data word.

17. The method as recited in claim 15, wherein said plurality of comparators is selected from the group consisting of operational amplifiers, logic gates and combinations thereof.

18. The method as recited in claim 15, wherein said plurality of comparators is eight exclusive OR logic gates.

19. An apparatus for framing data in a receive deserializer circuit, said apparatus comprising:

means for receiving serial data including a data reference pattern from a transmitter;

means for retiming said serial data to a recovered clock as sampled serial data;

means for deserializing said sampled serial data into a parallel data word timed to a word clock;

means for comparing said parallel data word with a preset data reference pattern until a match results;

means for generating a shift pulse when said comparing does not result in said match;

means for dividing said recovered clock into phase clocks, including said word clock; and

means for disabling said phase clocks for one bit period each time said shift pulse is generated, thereby creating a one bit shift in the alignment of said parallel data word being generated on said word clock in a demultiplexer.