Multi-standard channel decoder

• US 6,862,325 B2
• Filed: 10/17/2001
• Issued: 03/01/2005
• Est. Priority Date: 10/17/2000
• Status: Expired due to Term

• Current Assignee: Funai Electric Co., Ltd.
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Gay-Bellile, Olivier, Marchal, Xavier, Burns, Geoffrey Francis, Vaidyanathan, Krishnamurthy
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Pathak, Sudhanshu C.
• Application Number:
  US09/982,267
• Publication Number:
  US 20020070796A1
• Time in Patent Office: 1,231 Days
• Field of Search: 375/344, 712/36, 348/725, 455/247
• US Class Current: 375/340
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 2025/03522 Frequency domain
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03159 operating in the frequency domain H04L25/03165, H04L25/03178 take precedence
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4382 Demodulation or channel decoding, e.g. QPSK demodulation analog front ends or means for connecting modulators, demodulators or transceivers to a transmission line H04L27/0002
• CPC Class Codes: H04N 21/44209 Monitoring of downstream path of the transmission network originating from a server, e.g. bandwidth variations of a wireless network arrangements for maintenance or administration in data switching networks involving bandwidth and capacity management H04L41/0896
• CPC Class Codes: H04N 21/4435 Memory management allocation of memory to service a request G06F9/5016; addressing or allocating within memory systems or architectures G06F12/02
• CPC Class Codes: H04N 5/46 for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27

Abstract

The invention relates to a multi-standard digital receiver, in a digital video transmission system. It comprises a channel decoder for protecting a transmitted signal against channel transmission errors, the channel decoder comprising:

• • a set of co-processors including at least 3 clusters of programmable co-processors for executing the functions of a digital front-end block (DFE), a channel correction block (CHN) and a forward error correction block (FEC), respectively,
  • a general purpose processor (DSP) for managing control, synchronization and configuration of the channel decoder, and
  • a memory (SM) shared between the clusters and the general purpose processor.

Claims

1. A receiver, in a digital transmission system, comprising a channel decoder for protecting a transmitted signal against channel transmission errors, the channel decoder comprising:

a set of co-processors including at least 3 clusters of programmable co-processors for executing the functions of a digital front-end block (DFE), a channel correction block (CHN) and a forward error correction block (FEC), respectively,

a general purpose processor (DSP) for managing control, synchronization and configuration of the channel decoder, and

a memory (SM) shared between the clusters and the general purpose processor.

2. A receiver as claimed in claim 1, wherein the set of co-processors comprises:

a digital front-end processor (DFE) for computing;

base-band demodulation of the received signal,

a programmable Nyquist filter, and for controlling an automatic gain control loop (AGC) and synchronization loops for time and carrier recovery,

a fast Fourier transform processor (FFT) for performing demodulation in the case of multi-carrier systems and frequency domain equalization in the case of mono-carrier systems,

an adaptive filter array processor (AFA) for time domain equalization, interference rejection and frequency interpolation in the case of COFDM modulation,

a forward error correction processor (FEC) for decoding Reed-Solomon and convolutional codes which were used during transmission.

3. A broadcasting system comprising a receiver and a transmitter, in a digital video transmission system, wherein the receiver is according to any one of claim 1.

6. The receiver of claim 1, wherein the clusters of co-processors are programmable to allow for handling a plurality of data formats, and each respective cluster performs only a single one of the recited three functions.

4. In a digital video receiver, a method of channel decoding for protecting a transmitted signal against transmission errors, the method comprising the steps of base-band demodulation, channel correction and forward error correction of the received signal, each step being performed by a cluster of programmable co-processors, a general purpose processor with a shared memory being provided for managing control, synchronization and configuration of said clusters of co-processors.

5. A method of claim 4, wherein the method steps of base-band demodulation, channel correction and forward error correction is carried out by a set of instructions in a computer program product.

7. The method of claim 4, wherein the clusters of co-processors are programmable to allow for handling a plurality of data formats, and each respective cluster performs only a single one of the recited three steps.

8. The method of claim 5, wherein the clusters of co-processors are programmable for handling a plurality of data formats, and each respective cluster performs only a single one of the recited three steps.

9. A channel decoder for digital video data comprising:

an input for receiving signals in differing formats;

at least one first cluster comprising at least one first programmable co-processor for executing functions of a digital front-end block (DFE), which first cluster is programmable to adapt to all of the differing formats;

at least one a second cluster comprising at least one second programmable co-processors for executing functions of a channel correction block (CHN), which second cluster is programmable to adapt to all of the differing formats;

at least one a third cluster comprising at least one third programmable co-processor for executing functions of a forward error correction block (FEC), which third cluster is programmable to adapt to all of the differing formats;

a general purpose processor (DSP) for managing control, synchronization and configuration of the channel cluster; and

a memory (SM) shared between the processors.

10. The decoder of claim 9, wherein at least one of the processors is implemented in hardware.

11. The decoder of claim 9, wherein at least one of the processors is implemented in software.

12. The decoder of claim 9, wherein the decoder is adapted to receive a signal carrying a computer program for programming the processors.

13. The decoder of claim 9, wherein at least one of the first, second and third programmable co-processors comprises a cluster of co-processors.