Hardware I/O control block array for mirrored data transfers

• US 6,862,631 B1
• Filed: 02/12/2004
• Issued: 03/01/2005
• Est. Priority Date: 01/16/2002
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Young, B. Arlen
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): NGUYEN, TANH Q
• Application Number:
  US10/779,351
• Time in Patent Office: 383 Days
• Field of Search: 710/5, 710/20, 710/24, 710/39, 710/52, 710/53, 710/54, 710/56, 710/112, 714/1, 714/6, 707200-204
• US Class Current: 710/24
• CPC Class Codes: G06F 11/2087 with a common controller
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: Y10S 707/99953 Recoverability
• CPC Class Codes: Y10S 707/99955 Archiving or backup

Abstract

A single host adapter hardware I/O control block contains information used to specify a transfer of data from a host system to a first target device and in addition information that specifies whether the data is to be mirrored, and if so, optionally identifies a second target device on which the data is to be mirrored. After transferring the single hardware I/O control block to the host adapter integrated circuit, the host adapter integrated circuit determines whether the hardware I/O control block specifies a mirrored transaction. If a mirrored transaction is specified, the host adapter integrated circuit generates a second hardware I/O control block for the second target device using the information in the first hardware I/O control block. When the execution of both hardware I/O control blocks is complete, the host adapter integrated circuit provides a single completion notification to the host system.

Claims

1. A hardware I/O control block memory array comprising:

a first hardware I/O control block having a sister hardware I/O control block field; and

a second hardware I/O control block having a sister hardware I/O control block field wherein said sister hardware I/O control block field of said first hardware I/O control block includes a pointer to said second hardware I/O control block and said sister hardware I/O control block field of said second hardware I/O control block includes a pointer to said first hardware I/O control block, and said second hardware I/O control block includes information, other than said pointer to said first hardware I/O control block, copied from said first hardware I/O control block and further wherein said first and second hardware I/O control blocks are used for a mirrored data transaction.

2. The hardware I/O control block memory array as in claim 1 wherein when the pointer in the sister field of the first hardware I/O command block is a valid pointer upon completion of execution of said first hardware I/O control block, the sister field of said second hardware I/O control block is changed to an invalid pointer.

3. The hardware I/O control block memory array as in claim 1 wherein when the pointer in the sister field of the second hardware I/O command block is a valid pointer upon completion of execution of said second hardware I/O control block, the sister field of said first hardware I/O control block is changed to an invalid pointer.

4. The hardware I/O control block memory array as in claim 3 wherein said invalid pointer comprises a null identification number.

5. The hardware I/O control block structure stored in a memory as in claim 1 wherein said mirrored data transaction comprises a read transaction.

6. The hardware I/O control block structure stored in a memory as in claim 1 wherein said mirrored data transaction comprises a write transaction.

7. A system comprising:

a host adapter;

a plurality of target devices coupled to said host adapter; and

a memory coupled to said host adapter, and said memory having stored therein a hardware I/O control block memory array comprising;

a first hardware I/O control block having a sister hardware I/O control block field; and

a second hardware I/O control block having a sister hardware I/O control block field wherein said sister hardware I/O control block field of said first hardware I/O control block includes a pointer to said second hardware I/O control block and said sister hardware I/O control block field of said second hardware I/O control block includes a pointer to said first hardware I/O control block, and said second hardware I/O control block includes information, other than said pointer to said first hardware I/O control block, copied from said first hardware I/O control block and further wherein said first and second hardware I/O control blocks are used for a mirrored data transaction using at least two target devices in said plurality of target devices.

8. The system as in claim 7 wherein when the pointer in the sister field of the first hardware I/O command block is a valid pointer upon completion of execution of said first hardware I/O control block, the sister field of said second hardware I/O control block is changed to an invalid pointer.

9. The system as in claim 7 wherein when the pointer in the sister field of the second hardware I/O command block is a valid pointer upon completion of execution of said second hardware I/O control block, the sister field of said first hardware I/O control block is changed to an invalid pointer.

10. The system as in claim 8 wherein said invalid pointer comprises a null identification number.

11. The system as in claim 9 wherein said invalid pointer comprises a null identification number.

12. The system as in claim 7 wherein said mirrored transaction comprises a read transaction.

13. The system as in claim 7 wherein said mirrored transaction comprises a write transaction.