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Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching

  • US 6,864,041 B2
  • Filed: 05/02/2001
  • Issued: 03/08/2005
  • Est. Priority Date: 05/02/2001
  • Status: Expired due to Fees
First Claim
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1. A method of fabricating an electronic chip on a wafer, comprising:

  • developing on a surface of said wafer a first mask at a predetermined lower resolution; and

    etching said first mask under a first set of conditions for a predetermined period to achieve a higher resolution mask, said higher resolution achieving a critical dimension that is below 100 nm, said first set of conditions including a tuning parameter to independently control a line width variation tolerance of isolated features relative to nested features, wherein said critical dimension is between 75 nm and 100 nm.

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