Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching
First Claim
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1. A method of fabricating an electronic chip on a wafer, comprising:
- developing on a surface of said wafer a first mask at a predetermined lower resolution; and
etching said first mask under a first set of conditions for a predetermined period to achieve a higher resolution mask, said higher resolution achieving a critical dimension that is below 100 nm, said first set of conditions including a tuning parameter to independently control a line width variation tolerance of isolated features relative to nested features, wherein said critical dimension is between 75 nm and 100 nm.
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Abstract
A method of fabricating an electronic chip on a wafer in which a first mask at a predetermined lower resolution is developed on the wafer and then etched under a first set of conditions for a predetermined period to achieve a mask that is below the resolution limit of current lithography. The etched mask is then used as a hard mask for etching material on a lower layer.
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Citations
12 Claims
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1. A method of fabricating an electronic chip on a wafer, comprising:
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developing on a surface of said wafer a first mask at a predetermined lower resolution; and
etching said first mask under a first set of conditions for a predetermined period to achieve a higher resolution mask, said higher resolution achieving a critical dimension that is below 100 nm, said first set of conditions including a tuning parameter to independently control a line width variation tolerance of isolated features relative to nested features, wherein said critical dimension is between 75 nm and 100 nm. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of fabricating at least one electronic device or circuit on a wafer, comprising:
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developing a first mask on an outer surface of said wafer or of a layer of material deposited on said surface to define a pattern for at least part of a structure or circuit component for said electronic device or circuit, said first mask comprising an organic photo-sensitive resist material;
performing a trimming process on said first mask to adjust dimensions of said pattern, said trimming process achieving a critical dimension that is less than 100 nm; and
using said trimmed first mask as a hard mask for an etching process to remove material from at least one layer below said hard mask, wherein said trimming process includes a tuning parameter to independently control a line width variation tolerance of isolated fractures relative to nested features, wherein said critical dimension is between 75 nm and 100 nm. - View Dependent Claims (8, 9, 10)
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11. A method of controlling line width variation tolerances during fabrication of electronic devices or circuits on a wafer, comprising:
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developing a first mask on an outer surface of said wafer or of a layer of material deposited on said surface to define a pattern for at least part of a structure or circuit component for said electronic device or circuit, said first mask comprising an organic photo-sensitive resist material;
performing a trimming process on said first mask to adjust dimensions of features of said first mask, said trimmed process achieving a critical dimension that is less than 100 nm; and
using said trimmed first mask as a hard mask for an etching process to remove material from at least one layer below said hard mask, wherein said trimming process of said first mask comprises an oxygen and nitrogen plasma etch, in which;
a flow ratio of oxygen to nitrogen is between 0.25 and 2.5;
a setting of an RF power is in the range of 50 to 200 watts; and
a setting of a pressure is between 10 and 45 mTorr, and said critical dimension is between 75 nm and 100 nm.
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12. A method, during fabrication of electronic devices or circuits on a wafer, said devices or circuits having both isolated features and nested features, of controlling line width variation tolerances of said isolated features relative to said nested features while independently achieving a target critical dimension that is less than 100 nm, comprising:
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establishing a first set of conditions for an RF etch process that achieves said target critical dimension; and
controlling a level of said RF power as a parameter to independently control said line width variation tolerance of said isolated features relative to said nested features, wherein said first set of conditions comprises an oxygen and nitrogen plasma etch, in which;
a flow ratio of oxygen to nitrogen is between 0.25 and 2.5;
a setting of an RF power is in the range of 50 to 200 watts, and a setting of a pressure is between 10 and 45 mTorr, and said critical dimension is between 75 nm and 100 nm.
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Specification
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Current AssigneeInternational Business Machines Corporation
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Original AssigneeInternational Business Machines Corporation
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InventorsYang, Qingyun, Brown, Jeffrey J., Deshpande, Sadanand Vinayak, Horak, David V., Zhang, Ying, Surendra, Maheswaran, Tsou, Len Y., Yu, Chienfan
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Primary Examiner(s)Huff, Mark F.
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Assistant Examiner(s)BARRECA, NICOLE M
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Application NumberUS09/847,479Publication NumberTime in Patent Office1,406 DaysField of Search430/30, 430/311, 430/313, 430/316, 430/317, 430/329, 430/319, 438/714, 438/725, 216/49, 216/59, 216/67US Class Current430/316CPC Class CodesG03F 7/40 Treatment after imagewise r...G03F 7/427 using plasma means onlyH01L 21/0337 characterised by the proces...H01L 21/0338 Process specially adapted t...
