DRAM cell with enhanced SER immunity

• US 6,864,136 B2
• Filed: 12/11/2003
• Issued: 03/08/2005
• Est. Priority Date: 08/26/2002
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward J., Fried, David M., Brown, Jeffrey S., Rainey, Beth Ann
• Primary Examiner(s): Nhu, David
• Application Number:
  US10/733,671
• Publication Number:
  US 20040126969A1
• Time in Patent Office: 453 Days
• Field of Search: 438/239, 438/240, 438/241, 438/242, 438/244, 438/243, 438/246, 438/250, 438/248, 438/253, 438/266, 438/270, 438/278, 438/283, 438/305, 438/306, 438/311, 438/386, 438/381, 438/387, 438/393, 438/394, 438/396
• US Class Current: 438/239
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

A memory cell that has first and second fully depleted transfer devices each having a body region and first and second diffused electrodes. The cell has a differential storage capacitor having at least one node abutting and in electrical contact with one of the first and second diffused electrodes of each of the transfer devices. The storage capacitor has a primary capacitance and a plurality of inherent capacitances, wherein the primary capacitance has a capaictive value that is at least approximately five times greater than that of the plurality of inherent capacitances.

Claims

1. A method of forming a memory cell, comprising:

forming rails of semiconductor material on a substrate;

doping a first portion of said rails;

forming a dielectric on said first portion of at least every other one of said rails;

forming a plate electrode on said first portion of adjacent pairs of said rails;

forming an FET horizontally along a second portion of said rails adjacent to said first portion which contain the FET source and drain, said FET having a gate electrode disposed on all exposed sides of a part of said second portion of said rails.

2. The method of claim 1, wherein said substrate comprises a SOI substrate having a buried insulator layer, and wherein said rails are disposed on and contact said buried insulator layer.

3. The method of claim 1, wherein dielectic is formed on said first portions of all of said rails on which a memory cell is to be formed.

4. The method of claim 3, wherein said rails have a height of at least approximately 0.15 microns.