Method of making a MOS transistor

• US 6,864,178 B1
• Filed: 07/25/2003
• Issued: 03/08/2005
• Est. Priority Date: 07/25/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Kim, Young Pil
• Primary Examiner(s): Cao, Phat X.
• Assistant Examiner(s): Doan, Theresa T.
• Application Number:
  US10/627,059
• Time in Patent Office: 592 Days
• Field of Search: 438/297, 438/581, 438/592, 438/655, 438/660, 438663-664, 438/682
• US Class Current: 438/692
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66507 providing different silicide thicknesses on the gate and on source or drain
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method of making a MOS transistor is disclosed. The disclosed techniques can completely transform a polysilicon gate electrode into a metal silicide electrode through a brief thermal treatment process by extending the contact area between the polysilicide gate electrode and a metal layer prior to a formation of a metal silicide. The disclosed MOS transistor fabricating method comprises providing a semiconductor substrate further comprising a polysilicon gate electrode with a silicide layer thereon, a spacer, and source and drain regions with LDD regions; forming an insulating layer on the area of the substrate; polishing the insulating layer so that the top of the polysilicon gate electrode can be exposed; etching some part of the insulating layer and the spacer so that both lateral walls of the polysilicon gate electrode can be exposed; forming a metal layer on the substrate resulted from the preceding step so that the polysilicon gate electrode can be covered with the metal layer; and transforming completely the polysilicon gate electrode into a metal silicide gate electrode by performing a thermal treatment process.

Claims

1. A method of making a MOS transistor, the method comprising:

providing a semiconductor substrate comprising a polysilicon gate electrode with a silicide layer thereon, a spacer which is formed on both lateral walls of said polysilicon gate electrode, and source and drain regions with lightly doped drain regions which are formed at both sides of said polysilicon gate electrode;

forming an insulating layer on the area of said substrate including said polysilicon gate electrode;

polishing said insulating layer so that the top of said polysilicon gate electrode is exposed;

etching some part of said insulating layer and said spacer so that both lateral walls of said polysilicon gate electrode are exposed;

forming a metal layer on said substrate resulted from the preceding step so that said polysilicon gate electrode is covered with said metal layer; and

transforming completely said polysilicon gate electrode into a metal silicide gate electrode by performing a thermal treatment process for said substrate coated with said metal layer.

2. A method as defined by claim 1, wherein said spacer and said insulating layer comprise the same material.

3. A method as defined by claim 1, wherein said insulating layer and said spacer are etched until said polysilicon gate electrode is exposed to between about {fraction (4/6)} and about ⅚

of its height.

4. A method as defined by claim 1, wherein said metal layer comprises a multilayer including transition metals and their alloys.

5. A method as defined by claim 1, wherein said thermal treatment process comprises one or more steps of a rapid thermal process.

6. A method as defined by claim 1, wherein said thermal treatment process is performed at the temperature between about 400°

C. and about 600°

C. in a first step and between about 800°

C. and about 1000°

C. in a second step.