Semiconductor device and method for manufacturing the same

• US 6,864,532 B2
• Filed: 06/20/2002
• Issued: 03/08/2005
• Est. Priority Date: 01/14/2000
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Tsuzuki, Yukio, Aoki, Takaaki, Arakawa, Takafumi, Kuroyanagi, Akira, Suzuki, Mikimasa
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Dolan, Jennifer M
• Application Number:
  US10/175,294
• Publication Number:
  US 20020167046A1
• Time in Patent Office: 992 Days
• Field of Search: 257/244, 257/330, 257/332, 257/333, 257/334, 257/410, 257/411, 257/520, 257/559, 438/156, 438/206, 438/212, 438/216, 438/268, 438/287, 438/337, 438/591
• US Class Current: 257/330
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench-gate type transistor has a gate insulating film formed on an inner wall of a trench. The gate insulating film includes a first portion located on a wall of the trench and a second portion located on upper and bottom portions of the trench. The first portion includes a first oxide film, a nitride film, and a second oxide film. The second portion includes only an oxide film and is thicker than the first portion. Accordingly, electric field concentration on upper and lower corner portions of the trench can be reduced to improve the withstand voltage. In addition, and end of the trench may have an insulation layer that is thicker than the first portion.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a surface in which a trench is formed, wherein the trench has a wall;

a heavily doped region, which is formed in the wall at an end of the trench, wherein the heavily doped region is doped with an impurity to increase the oxidization speed of the heavily doped region;

a stack of films formed on the wall, wherein the stack includes;

a first silicon oxide film, wherein the thickness of the first silicon oxide film is greater at the end of the trench than elsewhere;

a silicon nitride film; and

a second silicon oxide film, and

a gate electrode formed on the films

an entrance silicon oxide film, the thickness of which is greater than that of the stack, wherein the entrance silicon oxide film is located at an entrance of the trench; and

a bottom film, the thickness of which is greater than that of the stack, wherein the bottom film is located at a bottom of the trench.

2. The semiconductor device of claim 1, wherein the substrate includes:

a source region of a first conduction type;

a base region of a second conduction type; and

a drift region of first conduction type, wherein the source region, the base region, and the drift region are located in this order from the surface and the trench extends perpendicularly from the surface to the drift region through the source region and the base region; and

a channel region in the base region adjacent to the trench.

3. The semiconductor device of claim 2, wherein the source region includes:

a first region, which has a predetermined impurity concentration and a predetermined depth; and

a second region, which has an impurity concentration that is lower than the first region, wherein the depth of the second region is greater than that of the first region, and the second region is located between the first region and the trench.

4. A semiconductor device comprising:

a semiconductor substrate having a surface in which a trench is formed, wherein the trench has a wall and an end;

a stack of insulating films formed on the wall, wherein the stack includes;

a first silicon oxide film;

a silicon nitride film, which is located on the first silicon oxide film; and

a second silicon oxide film, which is located on the silicon nitride film; and

an end insulating film formed at the end of the trench, wherein the end insulating film includes only the first and second silicon oxide films, and the thickness of the end insulating film is greater than that of the stack, and

a gate electrode formed on the stack and on the end insulating film

an entrance silicon oxide film, the thickness of which is greater than that of the stack, wherein the entrance silicon oxide film is located at an entrance of the trench; and

a bottom entrance film, the thickness of which is greater than that of the stack, wherein the bottom entrance film is located at a bottom of the trench.

5. The semiconductor device of claim 4, wherein the substrate includes:

a source region of a first conduction type;

a base region of a second conduction type; and

a drift region of first conduction type, wherein the source region, the base region, and the drift region are located in this order from the surface and the trench extends perpendicularly from the surface to the drift region through the source region and the base region; and

a channel region in the base region adjacent to the trench.

6. The semiconductor device of claim 5, wherein the source region includes:

a first region, which has a predetermined impurity concentration and a predetermined depth; and

a second region, which has an impurity concentration that is lower than the first region, wherein the depth of the second region is greater than that of the first region, and the second region is located between the first region and the trench.

7. A method for manufacturing a semiconductor device, in which a gate-insulating film is located on a wall of a trench formed in a semiconductor substrate, wherein a gate electrode is located on the gate-insulating film, the method comprising:

forming a heavily doped region in the wall at an end of the trench by doping an impurity with a concentration such that the oxidization speed of the doped region is increased;

oxidizing the trench surface to form a first silicon oxide film, which is thicker at the heavily doped region than elsewhere;

forming a silicon nitride film on the first silicon oxide film; and

oxidizing the trench surface to form a second silicon oxide film on the silicon nitride film; and

removing the silicon nitride film from an entrance and a bottom of the trench to form a silicon oxide film that is thicker than the stack.

8. The method of claim 7 further comprising:

forming a drift region of a first conduction type;

forming a base region of a second conduction type;

forming a source region of the first conduction type by forming a first region, which has a predetermined impurity concentration and a predetermined depth, and a second region, which has a lower impurity concentration and a greater depth than the first region; and

forming the trench to extend perpendicularly from the surface of the substrate to the drift region through the source region and the base region, such that the second region is located between the first region and the trench.

9. A method for manufacturing a semiconductor device, in which a gate-insulating film is located on a wall of a trench formed in a semiconductor substrate, wherein a gate electrode is located on the gate-insulating film, the method comprising:

forming a first silicon oxide film on the wall;

forming a silicon nitride film on the first silicon oxide film;

removing the silicon nitride film at an end of the trench;

oxidizing the wall to form a second silicon oxide film on the silicon nitride film and to thicken the first silicon oxide film at the end of the trench; and

removing the silicon nitride film from an entrance and a bottom of the trench to form a silicon oxide film that is thicker than the stack.

10. The method of claim 9 further comprising:

forming a drift region of a first conduction type;

forming a base region of a second conduction type;

forming a source region of the first conduction type by forming a first region, which has a predetermined impurity concentration and a predetermined depth, and a second region, which has a lower impurity concentration and a greater depth than the first region; and

forming the trench to extend perpendicularly from the surface of the substrate to the drift region through the source region and the base region, such that the second region is located between the first region and the trench.