Semiconductor wafer

• US 6,864,534 B2
• Filed: 08/16/2001
• Issued: 03/08/2005
• Est. Priority Date: 10/25/2000
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Matsumoto, Takuji, Ipposhi, Takashi
• Primary Examiner(s): Wilson, Allan R.
• Assistant Examiner(s): NGUYEN, JOSEPH H
• Application Number:
  US09/930,202
• Publication Number:
  US 20030094674A1
• Time in Patent Office: 1,300 Days
• Field of Search: 257/347, 257/627, 257/521, 257/622, 438/149, 438/479, 438/517
• US Class Current: 257/627
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 2223/54406 comprising alphanumeric information
• CPC Class Codes: H01L 2223/54493 Peripheral marks on wafers, e.g. orientation flats, notches, lot number
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

To provide a semiconductor wafer having crystal orientations of a wafer for the support substrate and a wafer for the device formation shifted from each other, wherein two kinds of wafers having different crystal orientations in which a notch or an orientation flat is to be provided do not need to be prepared. One of two semiconductor wafers having a notch or an orientation flat provided in the same crystal orientation <110> is set to be a wafer (1) for the support substrate and the other is set to be a wafer for the device formation. Both wafers are bonded with the notches or orientation flats shifted from each other (for example, a crystal orientation <100> of the wafer for the device formation and the crystal orientation <110> of the wafer (1) for the support substrate are set to the same direction). The wafer for the device formation is divided to obtain an SOI layer (3). A MOS transistor (TR1) or the like is formed on the SOI layer (3).

Claims

1. A semiconductor wafer comprising:

first and second semiconductor wafers having crystal orientation display sections to be nicks indicative of crystal orientations formed on fringes thereof,

wherein said crystal orientation display sections are indicative of an identical crystal orientation in said first and second semiconductor wafers, and

said first and second semiconductor wafers are bonded with said crystal orientation display sections shifted from each other.

2. The semiconductor wafer according to claim 1, wherein both of said first and second semiconductor wafers are (100) wafers in which (100) planes are main surfaces, and said crystal orientation display sections are shifted from each other by 45 degrees or 135 degrees.

3. The semiconductor wafer according to claim 2, wherein said first semiconductor wafer is a wafer for a support substrate and said second semiconductor wafer is a wafer for a device formation, and a main surface of said wafer for the device formation is provided with a semiconductor device including a MOS transistor in which a channel direction between a source and a drain is parallel with a direction of a crystal orientation <

100>

.

4. The semiconductor wafer according to claim 1, wherein said first semiconductor wafer is a wafer for a support substrate, said second semiconductor wafer is a wafer for an SQI layer, and an insulating film is formed on a main surface of at least one of said wafer for the support substrate and said wafer for the SQI layer.

5. A semiconductor wafer comprising:

a first semiconductor wafer; and

a second semiconductor wafer having a crystal orientation display section to be a nick indicative of a crystal orientation formed on a fringe,

wherein said first and second semiconductor wafers are bonded to each other such that a part of a main surface of said first semiconductor wafer is exposed by said crystal orientation display section of said second semiconductor wafer, and

printing is provided to said part of said main surface of said first semiconductor wafer.

6. The semiconductor wafer according to claim 5, wherein a crystal orientation display section to be a nick indicative of a crystal orientation is also formed on a fringe of said first semiconductor wafer, and said crystal orientation display section of said first semiconductor wafer and said crystal orientation display section of said second semiconductor wafer form an angle of 180 degrees.

7. The semiconductor wafer according to claim 5, wherein said first semiconductor wafer is a wafer for a support substrate, said second semiconductor wafer is a wafer for an SOI layer, and an insulating film is formed on a main surface of at least one of said wafer for the support substrate and said wafer for the SQI layer.

8. A semiconductor wafer comprising:

first and second semiconductor wafers having no buried insulating layer, said first and second semiconductor wafers including main suffaces to which a semiconductor that is a material of bulk structures is exposed,

wherein said main surfaces of said first and second semiconductor wafers are bonded with crystal orientations shifted from each other.

9. The semiconductor wafer according to claim 8, wherein both of said first and second semiconductor wafers are (100) wafers in which (100) planes are main surfaces, and said crystal orientations are shifted from each other by 45 degrees or 135 degrees.

10. The semiconductor wafer according to claim 9, wherein said first semiconductor wafer is a wafer for a support substrate and said second semiconductor wafer is a wafer for a device formation, and a main surface of said wafer for the device formation is provided with a semiconductor device including a MOS transistor in which a channel direction between a source and a drain is parallel with a direction of a crystal orientation <

100>

.