Programmable logic device

• US 6,864,710 B1
• Filed: 12/30/1999
• Issued: 03/08/2005
• Est. Priority Date: 12/30/1999
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Lacey, Timothy M., Johnson, David L.
• Primary Examiner(s): Tran, Anh Q.
• Application Number:
  US09/475,879
• Time in Patent Office: 1,895 Days
• Field of Search: 326 38- 41, 326/46, 326/47
• US Class Current: 326/39
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A programmable logic device comprising one or more horizontal routing channels, one or more vertical routing channels, and a logic element. Each logic element may be configured to connect between one of the horizontal routing channels and one of the vertical routing channels. The logic element may comprise a logic block cluster and a memory block.

Claims

1. A programmable logic device comprising:

one or more horizontal routing channels;

one or more vertical routing channels;

one or more logic elements each configured to (i) receive one or more inputs from one of said horizontal routing channels and one of said vertical routing channels and (ii) present one or more outputs to said horizontal routing channel and said vertical routing channel, wherein each of said logic elements comprises (i) a logic block array and (ii) an interconnect matrix coupled to said logic block array, said horizontal routing channel and said vertical routing channel, and

a memory block configured to (i) receive one or more inputs from and (ii) present one or more outputs to either (a) said interconnect matrix or (b) said horizontal routing channel and said vertical routing channel.

2. The programmable logic device according to claim 1, wherein said memory block comprises a first port connected to one of said horizontal routing channels and a second port connected to one of said vertical routing channels.

3. The programmable logic device according to claim 2, wherein said memory block is configured as a synchronous dual port memory.

4. The programmable logic device according to claim 2, wherein said memory block is configured as an asynchronous dual port memory.

5. The programmable logic device according to claim 2, wherein said memory block is configured as a synchronous FIFO memory.

6. The programmable logic device of claim 1, wherein said memory block is coupled to said interconnect matrix.

7. The programmable logic device of claim 1, further comprising a plurality of I/O blocks, wherein each I/O block of said plurality of I/O blocks is connected to a different end of said horizontal and said vertical routing channels.

8. The programmable logic device of claim 7, wherein said I/O blocks are grouped into I/O banks.

9. The programmable logic device of claim 7, wherein said I/O blocks comprise configurable I/O cells.

10. The programmable logic device of claim 1, further comprising one or more dedicated inputs for I/O cell control.

11. The programmable logic device of claim 1, further comprising one or more dedicated clock inputs.

12. The programmable logic device of claim 11, further comprising a phase lock loop circuit configured to generate one or more global clock signals in response to one or more input clock signals.

13. The programmable logic device of claim 10, wherein said dedicated inputs for I/O control comprise a reset input.

14. The programmable logic device of claim 10, wherein said dedicated inputs for I/O control comprise an output unable input.

15. The programmable logic device of claim 10, wherein said dedicated inputs for I/O control comprise a clock enable input.

16. The programmable logic device of claim 11, further comprising a phase lock loop circuit configured to generate one or more global clock signals by multiplying or dividing a frequency of a clock signal presented to said one or more dedicated clock inputs.

17. The programmable logic device of claim 1, wherein said logic block array comprises a plurality of logic blocks.

18. The programmable logic device of claim 17, wherein each logic block of said logic block array comprises a product term array configured to receive inputs from said interconnect matrix.

19. The programmable logic device of claim 18, wherein each of said logic blocks further comprise a plurality of macrocells each having an output coupled to said interconnect matrix.

20. The programmable logic device of claim 19, wherein each of said logic blocks further comprises an OR array coupling said product term array to said plurality of macrocells.

21. The programmable logic device of claim 1, wherein said interconnect matrix comprises a programmable interconnect matrix.

22. The programmable logic device of claim 6, wherein said interconnect matrix couples said memory block to one of said horizontal routing channels, one of said vertical routing channels, and said logic block array.

23. The programmable logic device of claim 1, comprising a plurality of horizontal routing channels and a plurality of vertical routing channels.

24. The programmable logic device of claim 1, comprising a plurality of logic elements.

25. The programmable logic device of claim 23, comprising at least four logic elements.

26. A programmable logic device comprising:

a plurality of horizontal routing channels;

a plurality of vertical routing channels;

a plurality of first memory blocks; and

a plurality of logic block arrays, wherein each of said plurality of first memory blocks and each of said plurality of logic block arrays is configured to (i) receive one or more inputs from one of said plurality of horizontal routing channels and one of said plurality of vertical routing channels and (ii) present one or more outputs to said horizontal routing channel and said vertical routing channel.

27. The programmable logic device according to claim 26, wherein each of said first memory blocks comprises a first port connected to one of said horizontal routing channels and a second port connected to one of said vertical routing channels.

28. The programmable logic device according to claim 26, wherein each of said first memory blocks is configurable to a mode selected from the group consisting of (i) an asynchronous dual port memory mode, (ii) a synchronous dual port memory mode, and (iii) a synchronous FIFO memory mode.

29. The programmable logic device of claim 26, wherein each of said logic block arrays comprises a plurality of programmably interconnected logic blocks, and each of said logic blocks comprises a plurality of macrocells.

30. The programmable logic device of claim 26, comprising:

M number of horizontal routing channels;

N number of vertical routing channels;

N times M number of first memory blocks; and

N times M number of logic block arrays, wherein N plus M is greater than or equal to 2.

31. The programmable logic device of claim 26, wherein each of said logic block arrays further comprises an interconnect matrix coupled to said horizontal routing channel and said vertical routing channel.

32. The programmable logic device of claim 31, wherein each of said logic block arrays further comprises a second memory block coupled to said interconnect matrix.