Thermally enhanced semiconductor package with EMI shielding

• US 6,865,084 B2
• Filed: 05/06/2003
• Issued: 03/08/2005
• Est. Priority Date: 02/07/2003
• Status: Expired due to Term

• Current Assignee: Siliconware Precision Industries Co., Ltd. (ASE Technology Holding Co., Ltd.)
• Original Assignee: Siliconware Precision Industries Co., Ltd. (ASE Technology Holding Co., Ltd.)
• Inventors: Tsai, Ho-Yi, Lin, Ying-Ren
• Primary Examiner(s): CHERVINSKY, BORIS LEO
• Application Number:
  US10/434,247
• Publication Number:
  US 20040156172A1
• Time in Patent Office: 672 Days
• Field of Search: 361/704, 361/707, 361/709, 361/818, 257/706, 257/712, 257/718, 257/787, 257/796, 174/35.R, 165/80.2, 165/80.3
• US Class Current: 361/704
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A thermally enhanced semiconductor package with EMI (electric and magnetic interference) shielding is provided in which a chip is mounted on and electrically connected to a surface of a substrate, and a thermally conductive member is stacked on the chip and electrically coupled to the surface of the substrate by bonding wires. An encapsulant is formed and encapsulates the chip, thermally conductive member, and bonding wires. A plurality of solder balls are implanted on an opposite surface of the substrate. The thermally conductive member is grounded via the bonding wires, substrate, and solder balls, and provides an EMI shielding effect for the chip to protect the chip against external electric and magnetic interference. The thermally conductive member has a coefficient of thermal expansion similar to that of the chip, and reduces thermal stress exerted on the chip and enhances mechanical strength of the chip to thereby prevent chip cracks.

Claims

1. A thermally enhanced semiconductor package with EMI shielding, comprising:

a substrate having an upper surface and a lower surface opposed to the upper surface;

at least one chip mounted on the upper surface of the substrate and electrically connected to the substrate by a plurality of first bonding wires;

a thermally conductive member attached to the chip and electrically coupled to the substrate by a plurality of second bonding wires; and

an encapsulant formed on the upper surface of the substrate for encapsulating the chip, first bonding wires, thermally conductive member, and second bonding wires.

2. The thermally enhanced semiconductor package of claim 1, further comprising:

a plurality of solder balls implanted on the lower surface of the substrate.

3. The thermally enhanced semiconductor package of claim 1, wherein the thermally conductive member has a coefficient of thermal expansion similar to that of the chip.

4. The thermally enhanced semiconductor package of claim 3, wherein the thermally conductive member is made of copper.

5. The thermally enhanced semiconductor package of claim 1, wherein the thermally conductive member has a first surface and a second surface opposed to the first surface, allowing the second surface to be in contact with the chip, and a metal layer is applied over predetermined portions on the first surface of the thermally conductive member and connected with the second bonding wires.

6. The thermally enhanced semiconductor package of claim 5, wherein the metal layer entirely or partly covers the first surface of the thermally conductive member.

7. The thermally enhanced semiconductor package of claim 5, wherein the metal layer is made of nickel/gold (Ni/Au) alloy or silver (Ag).

8. The thermally enhanced semiconductor package of claim 1, wherein the chip has an active surface and a non-active surface opposed to the active surface, allowing the non-active surface to be in contact with the substrate, and the active surface to abut against the thermally conductive member, and a plurality of bond pads are formed on the active surface of the chip at area free of being in contact with the thermally conductive member and connected with the first bonding wires.

9. The thermally enhanced semiconductor package of claim 2, wherein a plurality of bond fingers and a ground ring surrounding the bond fingers are formed on the upper surface of the substrate at area free of being in contact with the chip, allowing the bond fingers to be connected with the first bonding wires, and the ground ring to be connected with the second bonding wires.

10. The thermally enhanced semiconductor package of claim 9, wherein the substrate is formed with a plurality of conductive vias and ground vias penetrating therethrough, the conductive vias having one end thereof connected to the bond fingers and the other end connected to the corresponding solder balls, and the ground vias having one end thereof connected to the ground ring and the other end connected to the corresponding solder balls.

11. A thermally enhanced semiconductor package with EMI shielding, comprising:

a substrate having an upper surface and a lower surface opposed to the upper surface;

at least one chip mounted on the upper surface of the substrate and electrically connected to the substrate by a plurality of solder bumps;

a thermally conductive member having a first surface and a second surface opposed to the first surface, allowing the second surface to be attached to the chip and electrically coupled to the substrate by a plurality of bonding wires; and

an encapsulant formed on the upper surface of the substrate for encapsulating the chip, solder bumps, thermally conductive member, and bonding wires.

12. The thermally enhanced semiconductor package of claim 11, further comprising:

a plurality of solder balls implanted on the lower surface of the substrate.

13. The thermally enhanced semiconductor package of claim 11, wherein the thermally conductive member has a coefficient of thermal expansion similar to that of the chip.

14. The thermally enhanced semiconductor package of claim 13, wherein the thermally conductive member is made of copper.

15. The thermally enhanced semiconductor package of claim 11, wherein a metal layer is applied over predetermined portions on the first surface of the thermally conductive member and connected with the bonding wires.

16. The thermally enhanced semiconductor package of claim 15, wherein the metal layer entirely or partly covers the first surface of the thermally conductive member.

17. The thermally enhanced semiconductor package of claim 15, wherein the metal layer is made of nickel/gold (Ni/Au) alloy or silver (Ag).

18. The thermally enhanced semiconductor package of claim 15, wherein area on the first surface of the thermally conductive member free of forming the metal layer and bonding wires is exposed to outside of the encapsulant.

19. The thermally enhanced semiconductor package of claim 11, wherein the chip has an active surface and a non-active surface opposed to the active surface, allowing the non-active surface to be in contact with the thermally conductive member, and a plurality of bond pads are formed on the active surface of the chip and connected with the solder bumps.

20. The thermally enhanced semiconductor package of claim 12, wherein a plurality of bond pas are formed on the upper surface of the substrate at area mounted with the chip, and a ground ring is formed on the upper surface of the substrate outside the area for mounting the chip and is connected with the bonding wires.

21. The thermally enhanced semiconductor package of claim 20, wherein the substrate is formed with a plurality of conductive vias and ground vias penetrating therethrough, the conductive vias having one end thereof connected to the bond pads formed on the substrate and the other end connected to the corresponding solder balls, and the ground vias having one end thereof connected to the ground ring and the other end connected to the corresponding solder balls.