Method and apparatus for sampling digital data at a virtually constant rate, and transferring that data into a non-constant sampling rate device

• US 6,865,241 B1
• Filed: 12/15/1999
• Issued: 03/08/2005
• Est. Priority Date: 12/15/1999
• Status: Expired due to Term

• Current Assignee: Lexmark International Incorporated (Ninestar Corporation)
• Original Assignee: Lexmark International Incorporated (Ninestar Corporation)
• Inventors: Crutchfield, David Allen, Adkins, Christopher Alan
• Primary Examiner(s): Ghayour, Mohammad H.
• Assistant Examiner(s): Nguyen, Dung X.
• Application Number:
  US09/464,312
• Time in Patent Office: 1,910 Days
• Field of Search: 375/317, 375/338, 375/355, 375/872, 375/377, 710/1, 710/2, 710/3, 710/22, 708/313, 711/2, 711/101
• US Class Current: 375/372
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

An improved data acquisition system interface provides virtually constant sampling of input signals and provides those signals in a digitized format to a data acquisition unit that may not be able to sample at a constant rate without missing or “losing” some of the samples. The present invention acts as a front end interface that temporarily latches the sampled data, expands the data into multiple parallel signals, then stores the multiple parallel signals in a dual-port FIFO memory unit. Finally, the multiple parallel signals are transferred into the data acquisition unit at a lower frequency, and the transfer operations take place only when the data acquisition unit is ready to accept data. Since the front end misses no sampling intervals (i.e., it always takes a sample according to an extremely constant frequency crystal clock), then the data acquisition unit will be provided with all of these samples without losing any data. The only requirement is that the data throughput of the multiple parallel signals into the data acquisition unit be greater than or equal to the data sampling rate of the original signal at the front end. The present invention can be used with pure digital signals to capture their precise times of logic state transitions, or with serial data signals in which the precise moments of transition can be used to decipher the serial data. Moreover, the interface can be used with analog signals that are digitized using an analog-to-digital converter.

Claims

1. A constant rate sampling system, comprising:

expander logic that samples at least one input signal at a virtually constant rate, said expander logic containing at least one storage element for each of said at least one input signal, said expander logic receiving a data sample based on said at least one input signal upon an occurrence of a periodic event that occurs at said virtually constant rate, said expander logic temporarily storing at least one of said data samples for each of said at least one input signal, said expander logic having a first plurality of output data lines for each of said at least one input signal;

a plurality of memory elements that arc capable of being written to and read from, said first plurality of output data lines for each of said at least one input signal from said expander logic being in communication with said plurality of memory elements through which said at least one data sample for each of said at least one input signal is transferred into said plurality of memory elements, said plurality of memory elements having a second plurality of output data lines for each of said at least one input signal through which said at least one data sample for each of said at least one input signal is transferred out from said plurality of memory elements;

control logic which determines when said at least one data sample for each of said at least one input signal is transferred into said plurality of memory elements trough said first plurality of output data lines, and which determines when said at least one data sample for each of said at least one input signal is transferred out from said plurality of memory elements through said second plurality of output data lines;

said control logic causing said data transfer into said plurality of memory elements at first time intervals that occur less often than an occurrence of said periodic event at said virtually constant rate;

said control logic causing said data transfer out from said plurality of memory elements at second time intervals that occur less often than an occurrence of said periodic event at said virtually constant rate, in which said second time intervals may not be substantially consistent; and

wherein an effective throughput of said at least one data sample being transferred out from said plurality of memory elements at said second time intervals is greater than or equal to an effective throughput of said at least one input signal at said virtually constant rate.

2. The constant rate sampling system as recited in claim 1, wherein said effective throughput of said at least one data sample being transferred out from said plurality of memory elements at said second time intervals is equal to a number of data lines of said second plurality of output data lines used to carry each of said at least one input signal from said plurality of memory elements ties an effective frequency at which said second time intervals occur, and wherein said effective throughput of said at least one input signal at said virtually constant rate is substantially equal to said virtually constant rate.

3. The constant rate sampling system as recited in claim 2, further comprising a data acquisition device that receives said transferred signals from second plurality of output data lines that carry each of said at least one input signal out from said plurality of memory elements, wherein said second time intervals are dependent upon a receiving data rate capability of said data acquisition device in a form of a Device Ready handshake signal, and wherein said Device Ready signal does not always appear when expected at times when said data acquisition device is busy performing other tasks, yet all of said at least one data sample that are received by said expander logic eventually are transferred without loss into said data acquisition device, thereby enabling said data acquisition device to acquire all of said at least one data sample that are received by said expander logic regardless of its instantaneous presentation of said Device Ready signal.

4. The constant rate sampling system as recited in claim 3, wherein said control logic provides a Data Ready signal to said data acquisition device under a condition when said at least one data sample is currently stored within said plurality of memory elements, and thereafter said data acquisition device provides said Device Ready signal under a condition when said data acquisition device is available to receive data.

5. The constant rate sampling system as recited in claim 3, wherein said data acquisition device comprises a PCI plug-in card for a personal computer.

6. The constant rate sampling system as recited in claim 1, wherein said plurality of memory elements comprise one of:

random access memory, storage registers, ring buffers, or first in-first out buffers.

7. The constant rate sampling system as recited in claim 6, wherein said first in-first out buffers comprise a dual-port FIFO memory capable of receiving a first said at least one data sample at a Port A using a write operation, while simultaneously sending a second at least one data sample at a Port B using a read operation;

and wherein said write operation and read operation can occur at entirely different data rates and time intervals.

8. The constant rate sampling system as recited in claim 7, wherein said dual-port FIFO includes an AddrA I/O port, an AddrB I/O port, and said control logic provides an address pointer to a location within said plurality of memory elements at said AddrA I/O port to which one of said at least one data sample will be stored by said write operation, and said control logic provides an address pointer to a location within said plurality of memory elements at said AddrB I/O port to which one of sad at least one data sample will be retrieved by said read operation.

9. The constant rate sampling system as recited in claim 1, wherein said at least one storage element of said expander logic comprises at least one flip-flop and logic to hold one of said at least one data sample upon said periodic event that occurs at said virtually constant rate;

and upon an occurrence of one of said first time intervals, an output logic state of said at least one flip-flop is transferred to said first plurality of output data lines, and said at least one flip-flop is reset.

10. The constant rate sampling system as recited in claim 1, wherein said at least one storage element of said expander logic comprises “

i”

flip-flops, and said expander logic stores “

i”

sets of said at lent one data sample for each of said at least one input signal; and

upon an occurrence of one of said first time intervals, an output logic state of said “

i”

flip-flops is transferred to said first plurality of output data lines, regardless of a moment of transition of said periodic event that occurs at said virtually constant rate.

11. The constant rate sampling system as recited in claim 10, wherein said periodic event that occurs at said virtually constant rate is provided by a crystal clock oscillator operating at a clock frequency “

f1”

, said first time intervals are provided by a second clock operating at a clock frequency “

f2”

that is substantially equal to “

f1÷

i”

, and said second time intervals are provided by a third clock operating at a clock frequency “

f3”

that has an effective value over multiple sampling intervals that is greater than or equal to “

f1÷

i”

, so as to prevent said plurality of memory elements from exhibiting a data overflow.

12. The constant rate sampling system as recited in claim 1, wherein said at least one storage element of said expander logic comprises “

i−

1”

flip-flops, an said expander logic stores “

i−

1”

sets of said at least one data sample for each of said at least one input signal; and

upon an occurrence of one of said first time intervals, an output logic state of said “

i−

1”

flip-flops is transferred to said first plurality of output data lines along with another instantaneous of said at least one data sample for each of said at least one input signal upon an occurrence of a moment of transition of said periodic event that occurs at said virtually constant rate.

13. The constant rate sampling system as recited in claim 12, wherein said periodic event that occurs at said virtually constant rate is provided by a crystal clock oscillator operating at a clock frequency “

f1”

, said first time intervals are provided by a second clock operating at a clock frequency “

f2”

that is substantially equal to “

f1÷

1”

, and said second time intervals are provided by a third clock operating at a clock frequency “

f3”

that has an effective value over multiple sampling intervals that is greater than or equal to “

f1÷

i”

, so as to prevent said plurality of memory elements from exhibiting a data overflow.

14. The constant rate sampling system as recited in claim 1, wherein said control logic comprises one of:

a logic state machine, or a sequential processing circuit.

15. The constant rate sampling system as recited in claim 1, wherein said at least one input signal comprises a plurality of parallel digital input signals of a bus width “

n”

, each said at least one input signal thereby comprising a data block that is expanded by said expander logic such that said first plurality of output lines exhibits a bus size of “

i·

n”

.

16. The constant rate sampling system as recited in claim 1, wherein said at least one input signal comprises one of:

at least one digital input, or at least one serial input.

17. The constant rate sampling system as recited in claim 1, further comprising an analog-to-digital (A/D) converter that receives at least one analog input signal, said A/D converter having a plurality of digital outputs that as a group comprise said at least one input signal.

18. A method for sampling digital data at a virtually constant rate and transferring that data into a non-constant sampling rate data acquisition device, said method comprising:

receiving a digital input signal that changes state over time;

sampling a state of said digital input signal at a virtually constant sampling rate;

placing said sampled digital input signal into a storage element of a memory circuit, and continuing to gather at least one further sample of said digital input signal, hereby acquiring a plurality of samples of said digital input signal;

retrieving from said memory circuit said plurality of samples of said digital input signal, and transferring in one operation said plurality of samples of said digital input signal over a parallel bus to a data acquisition device that receives data at a non-constant rate, wherein said retrieving and transferring operations occur at time intervals less frequent than that of the virtually constant rate at which said digital input signal is sampled; and

wherein an effective throughput of said plurality of samples of said digital input signal into said data acquisition device is greater than or equal to an effective throughput of said digital input signal being sampled at said virtually constant rate, and thereby providing said non-constant sampling rate data acquisition device with data that is sampled at a said virtually constant rate.

19. The method as recited in claim 18, wherein memory circuit includes expander logic and a plurality of memory elements.

20. The method as recited in claim 19, wherein said expander logic comprises:

at least one flip-flop and logic to hold one of said sampled digital input signal; and

wherein said plurality of memory elements comprises one of random access memory, storage registers, ring buffers, or first in-first out buffers.

21. The method as recited in claim 18, wherein a receiving data rate capability of said data acquisition device, in a form of a Device Ready handshake signal, determines moments in time that data may be transferred into said data acquisition device, and wherein said Device Ready signal does not always appear when expected at times when said data acquisition device is busy performing other tasks, yet all of said digital input signal data samples that are received at said virtually constant rate eventually are transferred without loss into said data acquisition device, thereby enabling said data acquisition device to acquire all of said digital input signal data samples that are received at said virtually constant rate regardless of the instantaneous presentation of said Device Ready signal.

22. The method as recited in claim 21, wherein said data acquisition device comprises a PCI plug-in card for a personal computer.

23. The method as recited in claim 19, wherein said first in-first out buffers comprise a dual-port FIFO memory capable of receiving a first data sample of said digital input signal at a Port A using a write operation, while simultaneously sending a second data sample of said digital input signal at a Port B using a read operation;

and wherein said write operation and read operation can occur at entirely different data rates and time intervals.

24. The method as recited in claim 19, wherein said expander logic comprises “

i”

flip-flops, and said expander logic stores “

i”

sets of said digital input signal data samples; and

upon an occurrence of a first periodic clock signal, an output logic state of said “

i”

flip-flops is transferred to said plurality of memory elements, regardless of a moment of transition of a crystal clock oscillator that provides a second periodic clock signal at said virtually constant sampling rate.

25. The method as recited in claim 24, wherein said crystal clock oscillator operates at a clock frequency “

f1”

, said first periodic clock signal operates at a clock frequency “

f2”

that is substantially equal to “

f1÷

i”

, and a third periodic clock determines when said plurality of samples of said digital input are transferred to said data acquisition device, said third periodic clock operating at a clock frequency “

f3”

that has an effective value over multiple sampling intervals that is greater than or equal to “

f1÷

i”

, so as to prevent said plurality of storage elements from exhibiting a data overflow.

26. The method as recited in claim 19, wherein said expander logic comprises “

i−

1”

flip-flops, and said expander logic stores “

i−

1”

sets of said digital input signal data samples; and

upon an occurrence of a first periodic clock signal, an output logic state of said “

i−

1”

flip-flops is transferred to said plurality of memory elements along with another instantaneous sample of said digital input signal data samples, upon an occurrence of a moment of transition of a crystal clock oscillator that provides a second periodic clock signal at said virtually constant sampling rate.

27. The method as recited in claim 26, wherein said crystal clock oscillator operates at a clock frequency “

f1”

, said first periodic clock signal operates at a clock frequency “

f2”

that is substantially equal to “

f1+i”

, and a third periodic clock determines when said plurality of samples of said digital input are transferred to said data acquisition device, said third periodic clock operating at a clock frequency “

f3”

that has an effective value over multiple sampling intervals that is greater than or equal to “

f1÷

i”

, so as to prevent said plurality of storage elements from exhibiting a data overflow.

28. The method recited in claim 19, wherein said digital input signal comprises a plurality of parallel signals of a bus width “

n”

, each said digital input signal thereby comprising a data block that is expanded by said expander logic such that said parallel bus exhibits a bus size of “

i·

n”

.

29. The method as recited in claim 18, wherein said digital input signal comprises:

a one serial input signal.

30. The method as recited in claim 18, further comprising an analog-to-digital (A/D) converter that receives at least one analog input signal, said A/D converter having a plurality of digital outputs that as a group comprise said digital input signal.

31. A digital data sampling system, comprising:

expander logic that receives an input signal and samples said input signal at a virtually constant rate, said expander logic temporarily storing a plurality of samples of said input signal in latching elements, said expander logic being in communication with an intermediate data line for each of the expanded samples of said input signal; and

a plurality of memory elements that receive in a single operation and store said expanded samples of said input signal over said intermediate data lines, said memory elements having read and write capability, said memory elements being in communication with an output data line for each of the stored samples of said input signal, said memory elements storing said expanded samples of said input signal until a remote data receiving device is ready to receive data; and

upon that event, said memory elements transferring in a single operation said stored samples of said input signal over said output data lines into said remote data receiving device.

32. The digital data sampling system as recited in claim 31, further comprising:

control logic that transfers said stored samples of said input signal into said remote data receiving device less often than said expander logic samples said input signal at a virtually count rate, and wherein said transfers of said stored samples of said input signal into said remote data receiving device do not occur at a virtually constant rate;

however, an effective data throughput of said stored samples of said input signal into said remote data receiving device is greater than or equal to an effective throughput of samples of said input signal at said virtually constant rate.

33. The digital data sampling system as recited in claim 32, wherein said remote data receiving device comprises a data acquisition device, and wherein said transfers of said stored samples of said input signal into said remote data receiving device are dependent upon a receiving data rate capability of said data acquisition device in a form of a Device Ready handshake signal, and wherein said Device Ready signal does not always appear when expected at times when said data acquisition device is busy performing other tasks, yet all of said expanded samples of said input signal that are stored by said expander logic eventually are transferred without loss into said data acquisition device, thereby enabling said data acquisition device to acquire all of said samples of said input signal that are received by said expander logic regardless of its instantaneous presentation of said Device Ready signal.

34. The digital data sampling system as recited in claim 33, wherein said control logic provides a Data Ready signal to said data acquisition device under a condition when said at least one expanded sample of said input signal is currently stored within said plurality of memory elements, and thereafter said data acquisition device provides said Device Ready signal under a condition when said data acquisition device is available to receive data.

35. The digital data sampling system as recited in claim 33, wherein said data acquisition device comprises a PCI plug-in card for a personal computer.

36. The digital data sampling system as recited in claim 31, wherein said plurality of memory elements comprise one of random access memory, storage registers, ring buffers, or first in-first out buffers.

37. The digital data sampling system as recited in claim 36, wherein said first in-first out buffers comprise a dual-port FIFO memory capable of receiving one of said expanded samples of said input signal at a Port A using a write operation, while simultaneously sending a one of said stored samples of said input signal from a Port B using a read operation;

and wherein said write operation and read operation can occur at entirely different data rates and time intervals.

38. The digital data sampling system as recited in claim 37, wherein said dual-port FIFO includes an AddrA I/O port, an AddrB I/O port, and said control logic provides an address pointer to a location within said plurality of memory elements at said AddrA I/O port to which one of said expanded samples of said input signal will be stored by said write operation and said control logic provides an address pointer to a location within said plurality of memory elements at said AddrB I/O port to which one of said stored samples of said input signal will be retrieved by said read operation.

39. The digital data sampling system as recited in claim 31, wherein said expander logic comprises “

i”

flip-flops, and said expander logic stores “

i”

sets of said expanded samples of said input signal; and

an output logic state of said “

i”

flip-flops is transferred to said intermediate data lines in a single operation, regardless of a moment that said input signal is sampled into said expander logic at said virtually constant rate.

40. The digital data sampling system as recited in claim 31, wherein said expander logic comprises “

i−

1”

flip-flops, and said expander logic stores “

i−

1”

sets of said expanded samples of said input sign; and

an output logic state of said “

i−

1”

flip-flops is transferred to said intermediate data lines along with another instantaneous sample of said input signal in a single operation, which occurs at a moment of transition when said input signal is sampled into said expander logic at said virtually constant rate.

41. The digital data sampling system as recited in claim 32, wherein said control logic comprises one of:

a logic state machine, or a sequential processing circuit.

42. The digital data sampling system as recited in claim 31, wherein said input signal comprises a plurality of parallel digital input signals of a bus width “

n”

, and said input signal thereby comprising a data block that is expanded by a factor of “

i”

by said expander logic such that said intermediate data lines exhibit a bus size of “

i·

n”

.

43. The digital data sampling system as recited in claim 31, wherein said input signal comprises one of:

at least one digital input, or at least one serial input.

44. The digital data sampling system as recited in claim 31, further comprising an analog-to-digital (A/D) converter that receives at least one analog input signal, said A/D converter having a plurality of digital outputs that as a group comprise said input signal.