System and method for on-chip filter tuning

• US 6,865,381 B2
• Filed: 03/17/2003
• Issued: 03/08/2005
• Est. Priority Date: 11/12/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Bult, Klaas, Vorenkamp, Pieter, Carr, Frank
• Primary Examiner(s): Vuong, Quochien B.
• Application Number:
  US10/388,398
• Publication Number:
  US 20030162521A1
• Time in Patent Office: 722 Days
• Field of Search: 455/150.1, 455/191.1, 455/193.1, 455/280, 455/307, 333/167, 333/172, 327/552, 327/554, 327/555
• US Class Current: 455/307
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01F 27/34 Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H01F 27/42 Circuits specially adapted for the purpose of modifying, or compensating for, electric characteristics of transformers, reactors, or choke coils circuits for controlling transformers, reactors or choke coils, for the purpose of obtaining a desired output H02P13/00; impedance networks H03H
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 3/18 by means of synchronous gating arrangements
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03F 1/26 Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 1/3211 : in differential amplifiers
• CPC Class Codes: H03F 2200/111 : the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/294 : the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 : Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/447 : the amplifier being protected to temperature influence
• CPC Class Codes: H03F 2200/63 : the amplifier being suitable for CATV applications
• CPC Class Codes: H03F 2203/45264 : the dif amp comprising frequency or phase stabilisation means
• CPC Class Codes: H03F 2203/45286 : the temperature dependence of a differential amplifier being controlled
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 : Non-folded cascode stages
• CPC Class Codes: H03F 3/68 : Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 1/0023 : in emitter-coupled or cascode amplifiers H03G1/0029 takes precedence
• CPC Class Codes: H03G 1/0029 : using FETs
• CPC Class Codes: H03G 3/3052 : in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03H 11/04 : Frequency selective two-port networks
• CPC Class Codes: H03H 11/1291 : Current or voltage controlled filters
• CPC Class Codes: H03H 11/53 : simulating resistances; simulating resistance multipliers
• CPC Class Codes: H03H 11/54 : Modifications of networks to reduce influence of variations of temperature
• CPC Class Codes: H03H 19/004 : Switched capacitor networks
• CPC Class Codes: H03H 7/25 : comprising an element controlled by an electric or magnetic variable H03H7/27 takes precedence
• CPC Class Codes: H03J 1/0075 : where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 : Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 : by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 : with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 2207/06 : Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/103 : the additional signal being a digital signal
• CPC Class Codes: H03L 7/183 : a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

Claims

1. A method for tuning an actual filter using dummy filter in a receiver, comprising:

connecting an existing local oscillator (LO) signal to the dummy filter;

stimulating the dummy filter with the existing LO signal;

switching capacitors into the dummy filter until the center frequency of the dummy filter is that of the existing LO signal;

determining capacitor values for the actual filter to tune a response of the actual filter to a designed center frequency, the step of determining based on the capacitors switched into the dummy filter;

adding the capacitance values to the actual filter to center the response of the actual filter about the designed center frequency; and

disconnecting the existing LO from the dummy filter.

2. The method of claim 1, wherein the step of adding includes the step of switching capacitors into an inductor-capacitor circuit of the actual filter.

3. The method of claim 1, wherein the determining step includes the step of scaling a total capacitance switched into the dummy filter based on the ratio of the center frequency of the dummy filter relative to the designed center frequency of the actual filter.

4. The method of claim 3, wherein the step of scaling includes the step of scaling the total capacitance switched into the dummy filter according to the following equation (f₁/f₂)²·

C₁, where;

f₁ is the center frequency of the dummy filter;

f₂ is the center frequency of the actual filter; and

C₁ is the total capacitance switched into the dummy filter.

5. The method of claim 3, wherein the step of scaling includes the step of scaling the total capacitance switched into the dummy filter according to the following equation (f₁/f₂)²·

(L₁/L₂)·

C₁, where;

f₁ is the center frequency of the dummy filter;

f₂ is the center frequency of the actual filter;

L₁ is a total inductance in the dummy filter;

L₂ is a total inductance in the actual filter; and

C₁ is the total capacitance switched into the dummy filter.

6. A method for tuning an actual filter using dummy filter in a receiver, comprising:

connecting an existing local oscillator (LO) signal to the dummy filter;

stimulating the dummy filter with the existing LO signal;

determining a phase difference between an input of the dummy filter and an output of the dummy filter;

switching capacitors into the dummy filter based on the determined phase difference until the center frequency of the dummy filter is that of the existing LO signal;

determining capacitor values for the actual filter to tune a response of the actual filter to a designed center frequency, the step of determining based on the capacitors switched into the dummy filter;

adding the capacitance values to the actual filter to center the response of the actual filter about the designed center frequency; and

disconnecting the existing LO from the dummy filter.

7. The method of claim 6, wherein the switching step includes the step of switching capacitors into the dummy filter when the phase difference is greater than 0 degrees.

8. The method of claim 6, wherein the switching step includes the steps of:

starting a counter if the phase difference is greater than 0 degrees;

switching capacitors into the dummy filter responsive to an output of the counter; and

stopping the counter when the phase difference crosses 0 degrees.

9. The method of claim 8, wherein the adding step includes the step of switching in the capacitance values into the actual filter responsive to the output of the counter.

10. In an integrated circuit having a dummy filter and an actual filter, the dummy filter having a first bank of capacitors and the actual filter having a second bank of capacitors, a method of tuning a center frequency of the actual filter using the dummy filter, the method comprising:

stimulating the dummy filter with a local oscillator (LO) signal having a LO frequency;

tuning a center frequency of the dummy filter to the LO frequency, including the steps of,

determining a phase difference between an input of the dummy filter and an output of the dummy filter, and

switching capacitors into the dummy filter based on the determined phase difference until the center frequency of the dummy filter is aligned with the LO frequency; and

tuning the center frequency of the actual filter to a designed frequency including the steps of,

scaling a total capacitance switched into the dummy filter based on a ratio of the designed frequency to the LO frequency, and

switching capacitors from the second bank of capacitors into the actual filter based on the scaled total capacitance.

11. The method of claim 10, wherein the step of scaling includes the step of scaling the total capacitance switched into the dummy filter according to the following equation (f₁/f₂)²·

C₁, where;

f₁ is the center frequency of the dummy filter;

f₂ is the center frequency of the actual filter; and

C₁ is the total capacitance switched into the dummy filter.

12. The method of claim 10, wherein the step of scaling includes the step of scaling the total capacitance switched into the dummy filter according to the following equation (f₁/f₂)²·

(L₁/L₂)·

C₁, where;

f₁ is the center frequency of the dummy filter;

f₂ is the center frequency of the actual filter;

L₁ is a total inductance in the dummy filter;

L₂ is a total inductance in the actual filter; and

C₁ is the total capacitance switched into the dummy filter.

13. The method of claim 10, wherein the step of switching capacitors into the dummy filter includes the step of switching capacitors into the dummy filter when the phase difference is greater than 0 degrees.

14. The method of claim 10, wherein the step of switching capacitors into the dummy filter includes the steps of:

starting a counter if the phase difference is greater than 0 degrees;

switching capacitors into the dummy filter responsive to an output of the counter; and

stopping the counter when the phase difference crosses 0 degrees.

15. The method of claim 14, wherein the switching of capacitors from the second bank of capacitors into the actual filter is responsive to the output of the counter.