Apparatus and method for a reconfigurable pod interface for use with an emulator unit

• US 6,865,504 B2
• Filed: 08/05/2002
• Issued: 03/08/2005
• Est. Priority Date: 08/05/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hoar, Roland R., Swoboda, Gary L., Larson, Lee A., Deao, Douglas E.
• Primary Examiner(s): NGHIEM, MICHAEL P
• Application Number:
  US10/212,621
• Publication Number:
  US 20040024558A1
• Time in Patent Office: 946 Days
• Field of Search: 702/117, 702/119, 702/122, 702/123, 702/125, 703 13- 15, 703/23, 703/26, 703/27, 714 28- 30
• US Class Current: 702/123
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

A reconfigurable cable/pod unit replaces the cable/pod unit coupling an emulation unit and a target processor. The reconfigurable cable/pod unit includes the discrete logic elements, a programmable unit and interface logic. The programmable unit and the interface unit permit the pod unit to assign conductors to the coupled cable. The interface unit includes storage and other logic elements that compensate for the differences in clock speeds and in rates of data exchange between the emulation unit and the target processor. No changes are necessary in the emulation unit to use the reconfigurable cable/pod unit. The reconfigurable cable pod unit permits, by changing the programming in the programmable unit, to operate in selectable modes, to provide a selectable interface to the target processor, to implement changes and upgrades in the testing procedures, and to test different types of target processors.

Claims

1. A reconfigurable cable/pod unit for coupling an emulation unit with a target processor, the cable/pod unit comprising:

a first cable portion for coupling to the emulation unit;

a second cable portion for coupling to the target processor unit; and

a pod unit coupled to the first cable portion and the second cable portion, the pod unit including;

a programmable unit, the programmable unit responsive to program signals from the emulation unit, the program signals programming the programmable unit, the programmable unit assigning functionality to the conductors of the first and second cable portions in response to the program signals;

a discrete logic unit responsive to the programmable unit for receiving timing and control signals from the first and second cable portions, the discrete logic unit applying logic and control signals to the first and second cable portions; and

an interface unit responsive to the programmable unit for receiving and retransmitting data.

2. The cable/pod unit as recited in claim 1 wherein the first cable portion is designed to couple to a pre-existing cable.

3. The cable/pod unit as recited in claim 1 wherein the programmable unit is a field programmable gate array.

4. The cable/pod unit as recited in claim 1 wherein in a first programmed mode, the cable/pod unit exchanges only JTAG protocol and related signals between the emulation unit and the target processor.

5. The cable pod unit as recited in claim 1 wherein the cable/pod unit exchanges JTAG protocol, trace, and related signals simultaneously between the emulation unit and the target processor.

6. The cable/pod unit as recited in claim 1 wherein the cable pod unit exchanges only trace and related signals between the emulation unit and the target processor.

7. The cable/pod unit as recited in claim 1 wherein the programmable unit can be programmed by the program signals to provide a preselected interface to the target processor.

8. The cable/pod unit as recited in claim 1 wherein the programmable unit can be programmed by the program signals to provide an interface to a preselected target processor.

9. A method for providing reconfigurability for a cable/pod unit, the cable/pod unit coupled to a preexisting emulation unit by a first cable portion, the cable/pod unit coupled to a target processor unit by a second cable portion, the pod unit of the preexisting cable/pod unit having a discrete logic unit, the first and the second cable portions having a first and a second plurality of conductors respectively the method comprising:

to the preexisting pod unit of the cable/pod unit, adding a programmable unit, the programmable unit assigning the functionality to the first and second plurality of conductors;

to the preexisting pod unit adding an interface unit responsive to the programmable unit, the interface unit providing an interface between the emulation unit and the target processor unit, and

programming the programmable unit by the emulation unit.

10. The method as recited in claim 9 wherein the discrete logic unit provides an interface for timing and control signals between the emulation unit and the target processor unit.

11. The method as recited in claim 9 further comprising the step of programming the target processor unit to select only one mode between modes of operation consisting of 1.) exchanging only JTAG signals between the emulation unit and the target processor, 2.) exchanging only trace signals between the emulation unit and the target processor, and 3.) simultaneously exchanging JTAG and trace signals between the emulation unit and the target processor unit.

12. The method as recited in claim 9 further comprising the step of programming the programmable unit to provide a preselected interface with the target processor unit.

13. The method as recited in claim 9 further comprising the step of

programming the programmable unit to exchange signals with a plurality of predetermined target processor units.

14. A system for testing a target processor, the system comprising:

a preexisting emulation unit; and

a cable/pod unit, the cable/pod unit including;

a first cable portion coupled to the emulation unit;

a second cable portion coupled to the target processor; and

a pod unit coupled to the first cable portion and the second cable portion, the pod having;

a programmable unit, the programmable unit assigning the functionality of each of the conductors of the first and second cable portion;

an interface unit responsive to the programmable unit for providing an interface to the exchange of data between the first and second cable portions; and

a logic unit responsive to the programmable unit, the logic unit providing an interface between selected conductors of the first and second cable portions;

wherein the programmable unit is programmed by the emulation unit.

15. The system as recited in claim 14 wherein the cable/pod unit has a first mode of operation for exchanging JTAG and related signals between the emulation unit and the target processor, the cable pod unit having a second mode of operation for exchanging trace and related signals between the emulation unit and the target processor, and the cable pod unit having a third mode of operation for simultaneously exchanging JTAG, trace and related signals between the emulation unit and the target processor.

16. The system as recited in claim 14 wherein the cable/pod unit can provide a selectable interface to the target processor, the interface determined by the programming of the programmable unit.

17. The system as recited in claim 14 wherein the cable/pod unit can be programmed for interact with any of a predetermined plurality of target processors, the interaction with a particular target processor determined by a program in the programmable unit.