Memory card and system for updating distributed memory

• US 6,865,637 B1
• Filed: 06/26/2001
• Issued: 03/08/2005
• Est. Priority Date: 06/26/2001
• Status: Expired due to Term

• Current Assignee: Alcatel SA (Nokia Corporation)
• Original Assignee: Alcatel SA (Nokia Corporation)
• Inventors: Burger, Edwin J., Linares, Ignacio A., Gammenthaler, Robert S. Jr.
• Primary Examiner(s): Myers, Paul R.
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US09/891,999
• Time in Patent Office: 1,351 Days
• Field of Search: 710305-306, 710308-316, 710/38, 710/58, 710/61, 710300-304, 710/317, 709201-203, 709/248, 709215-219, 700/2, 700/5, 700/17, 700/20, 711147-150, 711161- 62, 711/173, 707/104, 707/10, 707/9, 370/258, 370/255, 370/257
• US Class Current: 710/305
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways

Abstract

A memory card cooperating with a network interface for receiving data entry and update signals from a database manager via a switch fabric and with a bus interface for outputting data on a system bus disposed in a system shelf, which shelf forms at least a portion of a telecommunications node having a distributed scalable database system. The memory card is operable to contain at least a portion of the distributed database in a high speed, high density memory block disposed thereon, which memory block is coupled to a network interface controller via a first memory interface and to a bus interface controller via a second memory interface. An arbiter is coupled to the first and second memory interfaces for arbitrating data input operations and data output operations with respect to the memory block.

Claims

1. A memory card, comprising:

a first interface controller operable to be coupled to a first interface, said first interface operating to receive database input signals;

a second interface controller operable to be coupled to a second interface, said second interface operating to couple said memory card to a bus;

a first memory interface disposed between said first interface controller and a memory block,

a second memory interface disposed between said memory block and said second interface controller; and

an arbiter coupled to said first and second memory interfaces for arbitrating data input operations and data output operations with respect to said memory block.

2. The memory card as set forth in claim 1, wherein said first interface comprises a network interface coupled to a switch fabric disposed in a telecommunications node.

3. The memory card as set forth in claim 1, further comprising an error correct module coupled to said memory block.

4. The memory card as set forth in claim 1, further comprising a synchronization logic block, said synchronization logic block operating, responsive to a data synchronization signal, to synchronize said data input operations with respect to said memory block with data input operations associated with another memory card.

5. The memory card as set forth in claim 1, wherein said memory block comprises at least one dynamic random access memory (DRAM) module.

6. The memory car as set forth in claim 1, wherein said memory block comprises at least one static random access memory (SRAM) module.

7. The memory card as set forth in claim 1, wherein said memory block comprises at least one high speed, high density non-volatile memory (NVM) module.

8. The memory card as set forth in claim 1, wherein said bus comprises a system bus operating to interconnect a plurality of processor cards disposed in a system shelf.

9. The memory card as set forth in claim 2, where said switch fabric comprises an Ethernet fabric.

10. The memory card as set forth in claim 8, wherein said system bus comprises a Compact Peripheral Component Interconnect (CPCI) bus.

11. The memory card as set forth in claim 8, wherein said system shelf forms at least a portion of a telecommunications node.

12. A system for updating a distributed database associated with a telecommunications node, comprising:

a database update manager for generating database update signals indicative at least of updated data; and

at least one memory card disposed in a system shelf forming a portion of said telecommunications node, said at least one memory card cooperating with a network interface for receiving said database update signals through a switch fabric, wherein said at least one memory card is operable to contain at least a portion of said distributed database in a memory block disposed thereon.

13. The system for updating a distributed database associated with a telecommunications node as set forth in claim 12, further comprising a synchronization signal generator associated with said database update manager, wherein said synchronization signal generator is operable to provide a data update synchronization signal for synchronizing said database update signals provided to a plurality of said memory cards.

14. The system for updating a distributed database associated with a telecommunications node as set forth in claim 12, wherein said database update manager is co-located with said telecommunications node.

15. The system for updating a distributed database associated with a telecommunications node as set forth in claim 12, wherein said switch fabric comprises an Ethernet fabric.

16. The system for updating a distributed database associated with a telecommunications node as set forth in claim 12, wherein said memory block comprises a dynamic random access memory (DRAM) module.

17. The system for updating a distributed database associated with a telecommunications node as set forth in claim 12, wherein said memory block comprises a static random access memory (SRAM) module.

18. The system for updating a distributed database associated with a telecommunications node as set forth in claim 12, wherein said memory block comprises a non-volatile memory (NVM) module.

19. The system for updating a distributed database associated with a telecommunications node as set forth in claim 12, wherein said at least one memory card comprises:

a network interface controller operable to be coupled to said network interface;

a bus interface controller operable to be coupled to a system bus interface, said system bus interface operating to couple said at least one memory card to a system bus;

first and second memory interfaces associated with said memory block, wherein said first memory interface is disposed between said network interface controller and said memory block and said second memory interface is disposed between said bus interface controller and said memory block; and

an arbiter coupled to said first and second memory interfaces for arbitrating data update operations and data output operations with respect to said memory block.

20. The system for updating a distributed database associated with a telecommunications node as set forth in claim 13, wherein said synchronization signal generator is integrated with said database update manager.

21. The system for updating a distributed database associated with a telecommunications node as set forth in claim 19, wherein said at least one memory card further comprises an error correct module coupled to said memory block.

22. The system for updating a distributed database associated with a telecommunications node as set forth in claim 19, wherein said system bus is operable to interconnect a plurality of processor cards.

23. The system for updating a distributed database associated with a telecommunications node as set forth in claim 22, wherein said system bus comprises a Compact Peripheral Component Interconnect (CPCI) bus.

24. A telecommunications node having a distributed database, comprising:

a database manager for generating signals indicative at least one of updating and entering data with respect to said distributed database;

a switch fabric interconnecting a plurality of system shelves; and

a memory card disposed in each system shelf, said memory card cooperating with a network interface for receiving said signals through said switch fabric and with a bus interface for outputting data on a system bus, wherein said memory card is operable to contain at least a portion of said distributed database in a memory block disposed thereon.

25. The telecommunications node having a distributed database as set forth in claim 24, wherein said switch fabric comprises an Ethernet fabric.

26. The telecommunications node having a distributed database as set forth in claim 24, further comprising a synchronization signal generator associated with said database manager, wherein said synchronization signal generator is operable to provide a data synchronization signal for synchronizing database input operations with respect to said memory cards.

27. The telecommunications node having a distributed database as set forth in claim 24, wherein said memory block comprises at least one dynamic random access memory (DRAM) module.

28. The telecommunications node having a distributed database as set forth in claim 24, wherein said memory block comprises at least one static random access memory (SRAM) module.

29. The telecommunications node having a distributed database as set forth in claim 24, wherein said memory block comprises at least one non-volatile memory (NVM) module.

30. The telecommunications node having a distributed database as set forth in claim 24, wherein said system bus comprises a bus segment operating to interconnect a plurality of processor cards.

31. The telecommunications node having a distributed database as set forth in claim 24, wherein said memory card comprises an error correct module coupled to said memory block.

32. The telecommunications node having a distributed database as set forth in claim 30, wherein said bus segment comprises a Compact Peripheral Component Interconnect (CPCI) bus segment.

33. The telecommunications node having a distributed database as set forth in claim 24, wherein said memory card comprises:

a network interface controller operable to be coupled to said network interface;

a bus interface controller operable to be coupled to said bus interface;

first and second memory interfaces associated with said memory block, wherein said first memory interface is disposed between said network interface controller and said memory block and said second memory interface is disposed between said bus interface controller and said memory block; and

an arbiter coupled to said first and second memory interfaces for arbitrating data input operations and data output operations with respect to said memory block.