Semiconductor device and method for fabricating the same

• US 6,867,106 B2
• Filed: 12/30/2002
• Issued: 03/15/2005
• Est. Priority Date: 10/25/2000
• Status: Expired due to Fees

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Yamaguchi, Seiichiro, Amano, Isao, Kai, Mitsuaki
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Yevsikov, Victor V
• Application Number:
  US10/330,113
• Publication Number:
  US 20030132464A1
• Time in Patent Office: 806 Days
• Field of Search: 438/331, 438/272, 438/589, 438/527, 438/682, 438/307, 438/270, 438/283
• US Class Current: 438/331
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The semiconductor device comprises: a conducting layer including: a channel region; a source region and a drain region sandwiching the channel region; and a body region connected to the channel region and being adjacent to the source region and the drain region; a gate electrode formed above the channel region interposing a gate insulation film therebetween; a dummy electrode formed on the body region near the interface between at least the drain region and the body region, and electrically insulated with the gate electrode; and a body contact region formed in the body region except a region where the dummy electrode is formed. The gate electrode and the dummy electrode are electrically insulated with each other, whereby the semiconductor device having body contacts can have a gate capacitance much decreased. Accordingly, deterioration of the speed performance of the transistors can be suppressed.

Claims

1. A method for fabricating a semiconductor device comprising the steps of:

forming on a first conduction type substrate a device isolation film for defining a device region including a first region and a second region adjacent to the first region;

forming above the device region a conducting film interposing a gate insulation film therebetween;

patterning the conducting film to form a gate electrode in the first region and a dummy electrode in the second region near the interface between the first region and the second region, the dummy electrode being electrically insulated with the gate electrode;

doping an impurity having a second conduction type different from the first conduction type in the first region with the gate electrode as a mask to form source/drain regions in the first region on both sides of the gate electrode; and

doping an impurity having the first conduction type in the second region with the dummy electrode as a mask to form a body contact region in the second region.

2. A method for fabricating a semiconductor device according to claim 1, further comprising the step of:

forming a silicide film selectively on the source/drain regions and body contact region except in a region between the gate electrode and the dummy electrode.

3. A method for fabricating a semiconductor device according to claim 2, further comprising the step of:

forming a sidewall insulation film on the side wall of the gate electrode and the side wall of the dummy electrode after the step of forming the gate electrode and the dummy electrode,

a gap between the gate electrode and the dummy electrode, and a width of the sidewall insulation film being controlled so as not to permit the silicide film to be formed between the gate electrode and the dummy electrode.

4. A method for fabricating a semiconductor device comprising the steps of:

forming on a first conduction type substrate a device isolation film for defining a device region including a first region and a second region adjacent to the first region;

depositing and patterning a first conducting film to form a gate electrode of the first conducting film above the first region;

depositing and patterning a second conducting film to form a dummy electrode of the second conducting film above the second region near the interface between the first region and the second region;

doping an impurity having a second conduction type different from the first conduction type in the first region with the gate electrode as a mask to form source/drain regions in the first region on both sides of the gate electrode; and

doping an impurity having the first conduction type in the second region with the dummy electrode as a mask to form a body contact region in the second region.

5. A method for fabricating a semiconductor device comprising the steps of:

forming on a first conduction type substrate a device isolation film for defining a device region including a first region and a second region adjacent to the first region;

forming a conducting film above the device region interposing a gate insulation film therebetween;

patterning the conducting film to form a gate electrode in the first region and a comb-shaped dummy electrode in the second region near the interface between the first region and the second region, the dummy electrode being formed integral with the gate electrode;

doping an impurity having a second conduction type different form the first conduction type in the first region with the gate electrode as a mask to form source/drain regions in the first region on both sides of the gate electrode;

doping an impurity having the first conduction type in the second region with the dummy electrode as a mask to form a body contact region in the second region.

7. A semiconductor device according to claim 5, further comprising the step of:

forming a silicide film selectively on the semiconductor layer except in gaps of the comb-shaped dummy electrode.

6. A method for fabricating a semiconductor device comprising the steps of:

forming on a first conduction type substrate a device isolation film for defining a device region including a first region and a second region adjacent to the first region;

forming a conducting film above the device region interposing a gate insulation film therebetween;

patterning the conducting film to form a gate electrode on the first region and a dummy electrode formed in a pattern having the inside cut out, formed on the second region near the interface between the first region and the second region, the dummy electrode being formed integral with the gate electrode;

doping an impurity having a second conduction type different from the first conduction type in the first region with the gate electrode as a mask to form source/drain regions in the first region on both sides of the gate electrode; and

doping an impurity having the first conduction type in the second region with the dummy electrode as a mask to form a body contact region in the second region.

8. A semiconductor device according to claim 6, further comprising the step of:

forming a silicide film selectively on the semiconductor layer except in a cut-out region of the dummy electrode.

9. A method for fabricating a semiconductor device comprising the steps of:

forming a device isolation film for defining a device region on a first conduction type substrate;

forming a gate electrode above the device region interposing a gate insulation film therebetween;

forming in the device region on both sides of the gate electrode a first impurity diffused region having a second conduction type different from the first conduction type, spaced from the device isolation film;

forming a first sidewall insulation film on the side wall of the gate electrode;

doping an impurity having the second conduction type in the device region with the gate electrode and the first sidewall insulation film as a mask to form a second impurity diffused region of the second conduction type which is deeper than the first impurity diffused region in the device region on both sides of the gate electrode.

10. A method for fabricating a semiconductor device according to claim 9, wherein

in the step of forming the first impurity diffused region, an impurity having the second conduction type is doped with a mask pattern having an opening of a width along extension of the gate electrode which is smaller than a width of the device region, and the gate electrode as a mask to thereby form the first impurity diffused region, spaced from the device isolation film.

11. A method for fabricating a semiconductor device according to claim 10, wherein

in the step of forming the device isolation film, a device region including a body contact region, and a lead-out region interconnecting a region below the gate electrode and the body contact region is formed, and the lead-out region is covered by the gate electrode and the first sidewall insulation film.

12. A method for fabricating a semiconductor device according to claim 9,

further comprising, after the step of forming the device isolation film, the step of forming a second sidewall insulation film covering the bordering edge of the device region,

in the step of forming the first impurity diffused region, the impurity having the second conduction type is doped with the gate electrode and the second sidewall insulation film as a mask to thereby form the first impurity diffused region, spaced from the device isolation film.

13. A method for fabricating a semiconductor device according to claim 12, wherein

in the step of forming the device isolation film, the device region including a body contact region, and a lead-out region interconnecting a region below the gate electrode and the body contact region, and the lead-out region is covered by the gate electrode, the first sidewall insulation film and the second sidewall insulation film.