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Fabrication method of sub-resolution pitch for integrated circuits

  • US 6,867,116 B1
  • Filed: 11/10/2003
  • Issued: 03/15/2005
  • Est. Priority Date: 11/10/2003
  • Status: Active Grant
First Claim
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1. A method of manufacturing a semiconductor device using a scanner, wherein the scanner is capable of realizing a minimum pitch, wherein the minimum pitch is the smallest possible pitch for the scanner, the method comprising:

  • providing a semiconductor substrate;

    forming a first layer over the semiconductor substrate;

    forming a second layer over the first layer;

    patterning the second layer to form a plurality of second layer patterns;

    patterning the first layer to form a plurality of first layer patterns, wherein a line width of the first layer patterns is greater than a line width of the second layer patterns, and each second layer pattern is located approximately over the center of a corresponding first layer pattern;

    performing a tone reversal to form a reversed tone for the second layer patterns; and

    etching the first layer patterns using the reversed tone as a mask, wherein the etched first layer patterns have a final pitch size, and wherein the final pitch is smaller than the minimum pitch.

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