Method for making an electronic component with self-aligned drain and gate, in damascene architecture

• US 6,867,128 B2
• Filed: 06/08/2001
• Issued: 03/15/2005
• Est. Priority Date: 06/09/2000
• Status: Expired due to Term

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation)
• Inventors: Deleonibus, Simon
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): Peralta, Ginette
• Application Number:
  US10/030,175
• Publication Number:
  US 20030008496A1
• Time in Patent Office: 1,376 Days
• Field of Search: 438/635, 438/785, 438/778, 438/630, 438/149, 438/151, 438/157, 438183- 5, 438/197, 438/201, 438/211, 438229- 33, 438257- 8, 438265- 6, 438/283, 438301- 7, 438/585, 438/591, 438/605, 438/618, 438/621, 438/626, 438648- 9, 438/595
• US Class Current: 438/635
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/76888 By rendering at least a portion of the conductor non conductive, e.g. oxidation
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for fabricating an electronic component with a self-aligned source, drain and gate. The method includes forming a dummy gate on a silicon substrate, in which the dummy gate defines a position for a channel of the component. The method also includes at least one implantation of doping impurities in the substrate, to form a source and a drain on either side of the channel, using the dummy gate as an implanting mask, superficial, self-aligned siliciding of the source and drain, depositing at least one contact metal layer having a total thickness greater than a height of the dummy gate, polishing the at least one contact metal layer stopping at the dummy gate, and replacing the dummy gate by at least one final gate separated from the substrate by a gate insulating layer, and electrically insulated from the source and drain. Further, depositing the at least one contact metal layer includes depositing a first metal layer and, above the first metal layer, a second metal layer having a greater mechanical resistance to polishing than the first metal layer. In addition, a thickness of the first metal layer is less than the height of the dummy gate, and a total thickness of the first and second layers is greater than the height of the dummy gate. Further, the first metal is chosen from among tungsten and titanium, and the second metal is chosen from among TaN, Ta and TiN.

Claims

1. A method for fabricating an electronic component with a self-aligned source, drain and gate, comprising the steps of:

a) forming a dummy gate on a silicon substrate, said dummy gate defining a position for a channel of the component;

b) at least one implantation of doping impurities in the substrate, to form a source and a drain on either side of the channel, using the dummy gate as an implanting mask;

c) forming a metal layer on the source, drain and dummy gate;

d) superficial, self-aligned siliciding of the source and drain by selectively siliciding the metal layer on the source and drain;

e) depositing at least one contact metal layer having a total thickness greater than a height of the dummy gate, polishing the at least one contact metal layer stopping at the dummy gate, and imparting an insulation characteristic to a surface region of the at least one contact metal layer and the metal layer on sides of the gate electrode; and

f) replacing the dummy gate by at least one final gate separated from the substrate by a gate insulating layer, and electrically insulated from the source and drain.

2. The method according to claim 1, wherein step e) comprises depositing a first metal layer and, above the first metal layer, a second metal layer having a greater mechanical resistance to polishing than the first metal layer, a thickness of the first metal layer being less than the height of the dummy gate, and a total thickness of the first and second metal layers being greater than the height of the dummy gate.

3. The method according to claim 2, wherein a metal of the first metal layer is chosen from among tungsten and titanium, and a metal of the second metal layer is chosen from among TaN, Ta and TiN.

4. The method according to claim 1, further comprising, before siliciding, forming side spacers on sides of the dummy gate.

5. The method according to claim 4, wherein the side spacers are formed comprising an attachment layer in silicon oxide, in contact with the dummy gate, and a superficial layer in silicon nitride.

6. The method according to claim 1, wherein the surface insulation comprises superficially oxidizing the at least one contact metal layer.

7. The method according to claim 1, wherein the silicon substrate comprises a solid substrate.

8. The method according to claim 1, wherein the silicon substrate comprises a silicon on insulator substrate.

9. The method according to claim 1, wherein step f) comprises removing the dummy gate, forming the gate insulating layer, depositing at least one metal layer to form the final gate, having an overall thickness equal to or greater than the height of the removed dummy gate.

10. The method according to claim 9, further comprising, after forming the gate insulating layer, depositing a first gate metal layer, depositing at least one inter-gate dielectric layer, and depositing a second gate metal layer.

11. The method according to claim 1, wherein the surface insulation comprises depositing a layer of dielectric material.