Semiconductor device and method for manufacturing the same

• US 6,867,431 B2
• Filed: 09/16/1994
• Issued: 03/15/2005
• Est. Priority Date: 09/20/1993
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sugawara, Akira, Suzuki, Atsunori, Konuma, Toshimitsu, Suzawa, Hideomi, Ohnuma, Hideto, Takemura, Yasuhiko, Uochi, Hideki, Zhang, Hongyong, Yamaguchi, Naoaki, Uehara, Yukiko
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US08/307,167
• Publication Number:
  US 20030100152A1
• Time in Patent Office: 3,833 Days
• Field of Search: 438/166, 438/486, 438/487, 257/66, 257/72, 257/57, 257/59, 257/408, 437/21, 437/40.TFT, 437/41.TFT, 437/44, 437/101
• US Class Current: 257/66
• CPC Class Codes: H01L 21/02145 the material containing aluminium, e.g. AlSiOx
• CPC Class Codes: H01L 21/02244 of a metallic layer
• CPC Class Codes: H01L 21/02258 formation by anodic treatment, e.g. anodic oxidation
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/31683 of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
• CPC Class Codes: H01L 21/31687 by anodic oxidation
• CPC Class Codes: H01L 21/321 After treatment
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD

Abstract

A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

Claims

1. A semiconductor device comprising:

a substrate;

at least one pixel electrode formed over the substrate;

at least one first thin film transistor electrically connected to the pixel electrode;

a peripheral circuit for driving the first thin film transistor, said peripheral circuit comprising at least one second thin film transistor and each of the first and second thin film transistors comprising;

a semiconductor film having source and drain regions, a channel region between the source and drain regions, and a pair of high resistivity regions between the channel region and the source and drain regions, respectively;

a gate insulating film adjacent to the channel region; and

a gate electrode adjacent to the channel region with the gate insulating film interposed therebetween,

wherein the pair of high resistivity regions is overlapped with the gate electrode at least partly in the second thin film transistor while there is no overlap between the pair of high resistivity regions and the gate electrode in the first thin film transistor.

2. A semiconductor device according to claim 1, wherein the gate electrode is located above the channel region.

3. A semiconductor device according to claim 1, wherein each of the first and second thin film transistors further comprises an anodic oxide film on at least a side surface of the gate electrode, the anodic oxide film of the second thin film transistor has a thinner thickness than that of the first thin film transistor.

4. A semiconductor device according to claim 1, wherein the semiconductor device is a liquid crystal display device.

5. A semiconductor device comprising:

a substrate;

at least one pixel electrode formed over the substrate;

at least one first thin film transistor electrically connected to the pixel electrode;

a peripheral circuit for driving the first thin film transistor, said peripheral circuit comprising at least one second thin film transistor and each of the first and second thin film transistors comprising;

a semiconductor film having source and drain regions, a channel region between the source and drain regions, and a pair of impurity regions between the channel region and the source and drain regions, respectively wherein a concentration of one conductivity type impurity contained in the pair of impurity regions is smaller than that in the source and drain regions;

a gate insulating film adjacent to the channel region; and

a gate electrode adjacent to the channel region with the gate insulating film interposed therebetween,

wherein the pair of impurity regions is overlapped with the gate electrode at least partly in the second thin film transistor while there is no overlap between the pair of impurity regions and the gate electrode in the first thin film transistor.

6. A semiconductor device according to claim 5, wherein the gate electrode is located above the channel region.

7. A semiconductor device according to claim 5, wherein each of the first and second thin film transistors further comprises an anodic oxide film on at least a side surface of the gate electrode, the anodic oxide film of the second thin film transistor has a thinner thickness than that of the first thin film transistor.

8. A semiconductor device according to claim 5, wherein the semiconductor device is a liquid crystal display device.

9. A semiconductor device according to claim 5, wherein the one conductivity type impurity is phosphorous.

10. A semiconductor device according to claim 5, wherein the one conductivity type impurity is boron.

11. A semiconductor device comprising:

a substrate;

at least one pixel electrode formed over the substrate;

at least one first thin film transistor electrically connected to the pixel electrode;

a peripheral circuit for driving the first thin film transistor, said peripheral circuit comprising at least one second thin film transistor and each of the first and second thin film transistors comprising;

a semiconductor film having source and drain regions, a channel region between the source and drain regions, and a pair of high resistivity regions between the channel region and the source and drain regions, respectively;

a gate insulating film adjacent to the channel region; and

a gate electrode located over the channel region with the gate insulating film interposed therebetween,

wherein the one conductivity type

wherein the pair of high resistivity regions is overlapped with the gate electrode at least partly in the second thin film transistor while there is no overlap between the pair of high resistivity regions and the gate electrode in the first thin film transistor, and

wherein the gate insulating film covers the channel region and the pair of high resistivity regions while the source and drain regions extend beyond side edges of the gate insulating film.

12. A semiconductor device according to claim 11, wherein each of the first and second thin film transistors further comprises an anodic oxide film on at least a side surface of the gate electrode, the anodic oxide film of the second thin film transistor has a thinner thickness than that of the first thin film transistor.

13. A semiconductor device according to claim 11, wherein the semiconductor device is a liquid crystal display device.

14. A semiconductor device comprising:

a substrate;

at least one pixel electrode formed over the substrate;

at least one first thin film transistor electrically connected to the pixel electrode;

a peripheral circuit for driving the first thin film transistor, said peripheral circuit comprising at least one second thin film transistor and each of the first and second thin film transistors comprising;

a semiconductor film having source and drain regions, a channel region between the source and drain regions, and a pair of impurity regions between the channel region and the source and drain regions, respectively wherein a concentration of one conductivity type impurity contained in the pair of impurity regions is smaller than that in the source and drain regions;

a gate insulating film adjacent to the channel region; and

a gate electrode located over the channel region with the gate insulating film interposed therebetween,

wherein the pair of impurity regions is overlapped with the gate electrode at least partly in the second thin film transistor while there is no overlap between the pair of impurity regions and the gate electrode in the first thin film transistor, and

wherein the gate insulating film covers the channel region and the pair of high resistivity regions while the source and drain regions extend beyond side edges of the gate insulating film.

15. A semiconductor device according to claim 14, wherein each of the first and second thin film transistors further comprises an anodic oxide film on at least a side surface of the gate electrode, the anodic oxide film of the second thin film transistor has a thinner thickness than that of the first thin film transistor.

16. A semiconductor device according to claim 14, wherein the semiconductor device is a liquid crystal display device.

17. A semiconductor device according to claim 14, wherein the one conductivity type impurity is phosphorous.

18. A semiconductor device according to claim 14, wherein the one conductivity type impurity is boron.

19. A semiconductor device comprising:

a substrate;

at least one pixel electrode formed over the substrate;

at least one first thin film transistor electrically connected to the pixel electrode;

a peripheral circuit for driving the first thin film transistor, said peripheral circuit comprising at least one second thin film transistor and each of the first and second thin film transistors comprising;

a semiconductor film having source and drain regions, a channel region between the source and drain regions, and a pair of high resistivity regions between the channel region and the source and drain regions, respectively;

a gate insulating film adjacent to the channel region; and

a gate electrode adjacent to the channel region with the gate insulating film interposed therebetween,

wherein the pair of high resistivity regions is overlapped with the gate electrode at least partly in the second thin film transistor while there is no overlap between the pair of high resistivity regions and the gate electrode in the first thin film transistor, and

wherein the source and drain regions of the first and second thin film transistors comprises nickel silicide.

20. A semiconductor device according to claim 19, wherein the gate electrode is located above the channel region.

21. A semiconductor device according to claim 19, wherein each of the first and second thin film transistors further comprises an anodic oxide film on at least a side surface of the gate electrode, the anodic oxide film of the second thin film transistor has a thinner thickness than that of the first thin film transistor.

22. A semiconductor device according to claim 19, wherein the semiconductor device is a liquid crystal display device.

23. A semiconductor device comprising:

a substrate;

at least one pixel electrode formed over the substrate;

at least one first thin film transistor electrically connected to the pixel electrode;

a peripheral circuit for driving the first thin film transistor, said peripheral circuit comprising at least one second thin film transistor and each of the first and second thin film transistors comprising;

a semiconductor film having source and drain regions, a channel region between the source and drain regions, and a pair of impurity regions between the channel region and the source and drain regions, respectively wherein a concentration of one conductivity type impurity contained in the pair of impurity regions is smaller than that in the source and drain regions;

a gate insulating film adjacent to the channel region; and

a gate electrode adjacent to the channel region with the gate insulating film interposed therebetween,

wherein the pair of impurity regions is overlapped with the gate electrode at least partly in the second thin film transistor while there is no overlap between the pair of impurity regions and the gate electrode in the first thin film transistor, and

wherein the source and drain regions of the first and second thin film transistors comprises nickel silicide.

24. A semiconductor device according to claim 23, wherein the gate electrode is located above the channel region.

25. A semiconductor device according to claim 23, wherein each of the first and second thin film transistors further comprises an anodic oxide film on at least a side surface of the gate electrode, the anodic oxide film of the second thin film transistor has a thinner thickness than that of the first thin film transistor.

26. A semiconductor device according to claim 23, wherein the semiconductor device is a liquid crystal display device.

27. A semiconductor device according to claim 23, wherein the one conductivity type impurity is phosphorous.

28. A semiconductor device according to claim 23, wherein the one conductivity type impurity is boron.