Lead frame structure with aperture or groove for flip chip in a leaded molded package

• US 6,867,481 B2
• Filed: 04/11/2003
• Issued: 03/15/2005
• Est. Priority Date: 04/11/2003
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Joshi, Rajeev, Wu, Chung-Lin
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US10/411,688
• Publication Number:
  US 20040201081A1
• Time in Patent Office: 704 Days
• Field of Search: 257/666, 257/667, 257669-672, 257/674, 257/676, 257/696, 257/698, 257/730
• US Class Current: 257/666
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/37011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/37099 Material
• CPC Class Codes: H01L 2224/40095 Kinked
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/73255 Bump and strap connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/84 using a strap connector
• CPC Class Codes: H01L 2224/92226 the second connecting process involving a strap connector
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

Claims

1. A semiconductor die package comprising;

(a) a semiconductor die including a first surface and a second surfaces, wherein the first surface comprises a source region and a gate region, and the second surface comprises a drain region;

(b) a leadframe structure comprising a die attach region and a plurality of leads extending away from the die attach region, wherein the die attach region includes one or more apertures extending through the die attach region and being oriented generally perpendicular to the orientations of the leads in the plurality of leads, and wherein the semiconductor die is mounted on the die attach region of the leadframe structure and wherein the first surface of the semiconductor die is proximate to the leadframe structure and the second surface of the semiconductor die is distal to the leadframe structure;

(c) a plurality of solder joints coupling die semiconductor die to the leadframe structure, wherein an aperture in the one or more apertures is between adjacent solder joints;

(d) a molding material that is around at least portions of the die attach region of the leadframe structure and the semiconductor die, and wherein the molding material is also within the one or more apertures in the die attach region of the lead frame structure; and

(e) a drain clip coupled to the second surface of the semiconductor die.

2. The semiconductor die package of claim 1, wherein the die attach region further includes a plurality of grooves formed in the leadframe structure.

6. The semiconductor die package of claim 1 wherein the one or more apertures are under the semiconductor die.

3. A semiconductor die package comprising:

(a) a semiconductor die including a first surface comprising a source region and a gate region and a second surface comprising a drain region;

(b) a leadframe structure comprising a die attach region and a plurality of leads extending away from the die attach region, wherein the die attach region includes one or more grooves in the die attach region, and wherein the semiconductor die is mounted on the die attach region of the leadframe structure using solder joints that are disposed in the one or more grooves, wherein the solder joints couple the source region to the leadframe structure and the gate region to the leadframe structure;

(c) a molding material that is around at least portions of the die attach region of the leadframe structure and the semiconductor die wherein the die attach region comprises at least one aperture extending through the die attach region; and

(d) a drain clip coupled to the drain region.

4. The semiconductor die package of claim 3 wherein the aperture is in the form of a slot, the slot being oriented generally perpendicular to the leads in the plurality of leads.

5. The semiconductor die package of claim 3 wherein the aperture is in the form of a slot, the slot being oriented generally parallel to the leads in the plurality of leads.

7. The semiconductor die package of claim 3 wherein at least one aperture is in the die attach region and under the semiconductor die.