Semiconductor packaging

• US 6,867,499 B1
• Filed: 10/02/2000
• Issued: 03/15/2005
• Est. Priority Date: 09/30/1999
• Status: Expired due to Term

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Tabrizi, Behnam
• Primary Examiner(s): Eckert, George
• Assistant Examiner(s): Chu, Chris C.
• Application Number:
  US09/677,291
• Time in Patent Office: 1,625 Days
• Field of Search: 257/666, 257/667, 257/673, 257/676, 257684-687, 257/704, 257/762, 257/763, 257/766, 257/777, 257/782, 438/108, 438/109, 361/760
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/2518 being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15156 : Side view
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

An electronic component and a method for making an electronic component are disclosed. The electronic component has a silicon package. The silicon package has a recess formed thereon in which a conductive region is placed. A bare die electronic device is disposed in the recess. The device has a top, a bottom, sides and a plurality of terminals, including a non-top terminal. The non-top terminal is electrically coupled to the conductive region. The electronic component is constructed by first creating a recess in a silicon wafer to a depth substantially equal to the first dimension of the bare die electronic device. A conductive material is applied to the recess. The electronic device is inserted into the recess so that the bottom terminal is coupled to the conductive material. A dielectric or other planarizing material is applied into the recess. Top and bottom contacts are then applied to form the electronic component so that it may be used as a ball grid array package. The top contact is electrically coupled to the top terminal of the electronic device and the bottom contact is coupled electrically to the conductive material.

Claims

1. An electronic component comprising:

an electronic device package formed from an integral silicon wafer having a recess, the recess including a single conductive region, the wafer and the conductive region conductively coupled so as to be at substantially the same electrical potential;

a bare die electronic device having a top, a bottom, sides, and a plurality of terminals, including a non-terminal, the device being disposed in the recess and physically coupled to the package by a conductive bonding material, and wherein the non-top terminal is electrically coupled to the conductive region by the conductive bonding material; and

a dielectric material disposed so as to form a planar surface over the recess that is level with or higher than the top of the device, the dielectric material filling the recess not occupied by the device and conductive bonding material.

2. An electronic component according to claim 1, wherein:

the conductive region is formed by metallization.

3. An electronic component according to claim 1, wherein the conductive region comprises:

a first layer of titanium;

a second layer of copper deposited on the first layer; and

a third layer of chrome deposited on the second layer.

4. An electronic component according to claim 1, further comprising:

a plurality of metallized bumps in a plane, wherein each terminal is electrically coupled to at least one bump, and each bump is electrically coupled to at most one electrically distinct terminal.

5. An electronic component according to claim 4, wherein:

the package includes a top and a bottom; and

the bumps are located above the top of the package.

6. An electronic component according to claim 1, wherein the device is a vertical device and the bottom of the device is coupled to the recess.

7. An electronic component according to claim 1, further comprising:

a second conductive region coupled to a terminal other than the non-top terminal.

8. An electronic component according to claim 7 wherein the second conductive region is non-wire bonded.

9. An electronic component according to claim 1, a plurality of contacts including at least a first contact and a second contact, the first contact being electrically coupled to the non-top terminal and the second contact being electrically coupled to a terminal other than the non-top terminal.

10. An electronic component according to claim 9, wherein the plurality of contacts reside in the same plane.

11. An electronic component according to claim 9, further comprising:

a second layer of dielectric completely covering the silicon wafer and the device except for the plurality of contacts.

12. An electronic component comprising:

an electronic component package formed from an integral silicon wafer having a recess, the recess including a first and only conductive region, the wafer and the first conductive region conductively coupled so as to be at substantially the same electrical potential; and

a bare die electronic device having a top, a bottom, sides, and a plurality of terminals, including a non-top terminal and a top terminal, the device being disposed in the recess and physically coupled to the package by a conductive bonding material, wherein the non-top terminal is electrically coupled to the first conductive region by the conductive bonding material, and the top terminal is electrically coupled to a second conductive region; and

a dielectric material disposed over the recess such that at least a portion of the first and second conductive regions are essentially planar, the dielectric material filling the recess not occupied by the device and conductive bonding material.

13. An electronic component according to claim 12, wherein:

the second conductive region is a solder bump.

14. An electronic component comprising:

an electronic device package formed from an integral silicon wafer having a recess, the recess including a single conductive region, the wafer and the single conductive region conductively coupled so as to be at substantially the same electrical potential;

an electronic device having a top, a bottom, sides, and a plurality of terminals, including a non-top terminal located in a region other than the top of the device, the device being disposed in the recess and physically coupled to the package by a conductive bonding material, wherein the non-top terminal is electrically coupled to the conductive region by the conductive bonding material; and

a layer of insulation disposed so as to form a planar surface over the recess that is level with or higher than the top of the device, the layer of insulation filling the recess not occupied by the device and conductive bonding material.

15. An electronic component according to claim 14, wherein:

one of the terminals of the device is a top contact located at the top of the device; and

the package has a package top, wherein the package top also includes a contact coupled electrically via the conductive region to the non-top terminal.

16. A component according to claim 14, wherein:

the conductive region comprises a layer of metal; and

the electronic device resides within the recess and the metal is electrically coupled to the non-top terminal of the device.

17. An electronic component according to claim 16, wherein the metal of the conductive region extends to a portion of the package top, the electronic component further comprising:

a bottom contact electrically coupled to the metal on the package top.

18. An electronic component according to claim 14, wherein the layer of insulation is a dielectric.

19. An electronic component comprising:

an electronic device having a first terminal and a second terminal, wherein a first dimension is defined therebetween;

an electronic device package having a first surface, the package formed from an integral silicon wafer having a recess on the first surface that has a depth that is substantially equal to the first dimension, the package further having a layer of metal applied to the recess and to a portion of the first surface, wherein the electronic device resides within the recess and is physically coupled to the package by a conductive bonding material, the second terminal is electrically coupled to the layer of metal by the conductive bonding material, and the layer of metal and the wafer are conductively coupled so as to be at substantially the same electrical potential; and

a layer of insulation disposed so as to form a planar surface over the recess that is level with or higher than the top of the device, the layer of insulation filling the recess not occupied by the device and conductive bonding material.

20. An electronic component according to claim 19, further comprising:

a first contact coupled to the first terminal; and

a second contact coupled to the metal residing on the first surface of the package.

21. An electronic component comprising:

a non-molded electronic component package having a package top and formed from an integral silicon wafer including a recess;

a bare die electronic device having a top, a bottom, sides, and a plurality of contacts, the device being disposed in the recess and physically coupled to the package by a conductive bonding material, wherein at least one of the plurality of contacts is electrically coupled by the conductive bonding material to a metallization layer, the wafer and the metallization layer conductively coupled so as to be at substantially the same electrical potential; and

a planarizing material filling the recess not occupied by the device and conductive bonding material to substantially create a level plane that includes the package top.

22. An electronic component according to claim 21, further comprising:

a second metallization layer coupling one contact to a redistribution point on the package top, wherein each contact remains electrically distinct.

23. An electronic component according to claim 22, further comprising:

a plurality of conductive bumps, each bump being disposed at a redistribution point.

24. The electronic component according to claim 23, such that the conductive bumps are spaced for electrically coupling with a pre-printed circuit board.

25. The electronic component according to claim 24, wherein the electronic component is a flip chip.

26. An electronic component comprising:

an electronic device package formed from an integral silicon wafer having a recess, the recess including a single conductive region, the wafer and the conductive region conductively coupled so as to be at substantially the same electrical potential;

a bare die electronic device having a top, a bottom, sides, and a plurality of terminals, including a non-top terminal, the device being disposed in the recess and physically coupled to the package by a conductive bonding material, and wherein the non-top terminal is electrically coupled to the conductive region by the conductive bonding material;

a planarizing material filling the recess not occupied by the device and conductive bonding material to substantially create a level plane that includes the package top; and

a plurality of contacts including at least a first contact and a second contact, the first contact being electrically coupled to the non-top terminal and the second contact being electrically coupled to a terminal other than the non-top terminal, wherein the plurality of contacts reside in the level plane.

27. An electronic component comprising:

a silicon wafer having a recess;

a bare die electronic device having first and second contacts, the device being disposed in the recess and physically coupled to the wafer by a conductive bonding material, the first contact electrically coupled by the conductive bonding material to an electrically conductive region, the electrically conductive region electrically coupling the first contact and the wafer to an electrical input of the electronic component, wherein the second contact is electrically coupled by non-wire bonding to a second electrical input of the electronic component, and

a dielectric material disposed so as to form a planar surface over the recess that is level with or higher than the top of the device, the dielectric material filling the recess not occupied by the device and conductive bonding material.

28. An electronic component according to claim 27, wherein the bare die electronic device is covered by the dielectric material and the electronic component is a flip chip.

29. The electronic component according to claim 28, wherein the silicon wafer is an integral piece of silicon.