Semiconductor device

• US 6,867,502 B2
• Filed: 02/21/2003
• Issued: 03/15/2005
• Est. Priority Date: 03/08/2002
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Usami, Masami, Ujiie, Kenji, Katagiri, Mitsuaki
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Tran, Thanh Y.
• Application Number:
  US10/369,764
• Publication Number:
  US 20030168748A1
• Time in Patent Office: 753 Days
• Field of Search: 257/778, 257737-738, 438/108, 438613-617, 228/180.22
• US Class Current: 257/778
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05085 with additional elements, e.g. vias arrays, interposed between the stacked layers
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A flip-chip BGA is disclosed which exhibits an excellent high-speed electric transmission characteristic while minimizing the formation of voids in sealing resin filled between a semiconductor chip and a wiring substrate. A silicon chip is flip-chip-mounted on a package substrate, and in a central area of a main surface of the silicon chip are arranged a power supply circuit, an input/output circuit, and plural bonding pads, while in the other area than the central area are arranged solder bumps in a matrix form, the solder bumps being electrically connected to the bonding pads through Cu wiring. Of the solder bumps, solder bumps for input/output power supply and solder bumps for the input and output of a data signal are arranged in a first area adjacent to the central area, and solder bumps for address signal input are arranged in a second area located outside the first area.

Claims

1. A semiconductor device in which a semiconductor chip is flip-chip-mounted over a wiring substrate through a plurality of bump electrodes formed over a main surface of the semiconductor chip,

wherein a power supply circuit, an input/output circuit, and a plurality of pads are arranged in a central area of the main surface of the semiconductor chip,

wherein the plurality of bump electrodes are arrayed in an area than the central area of the main surface of the semiconductor chip, the bump electrodes being electrically connected to the pads by metal wirings,

wherein the plurality of bump electrodes include bump electrodes functionally connected with an input/output power supply, an input and output of a data signal, and an input of an address signal,

wherein, of the plural bump electrodes, those for the input/output power supply and those for the input and output of a data signal are mainly arranged in a first area adjacent to the central area of the main surface of the semiconductor chip,

wherein, of the plural bump electrodes, those for the input of an address signal are mainly arranged in a second area located outside the first area,

wherein a gap between the semiconductor chip and the wiring substrate is filled with a sealing resin, and

wherein lands integral with the metal wirings and to which the bump electrodes are not connected are arranged in the second area.

2. A semiconductor device according to claim 1, wherein, between the first and the second area of the semiconductor chip, a third area is provided in which a portion of the metal wirings which connect the bump electrodes for the input of an address signal to the pads is disposed.

3. A semiconductor device according to claim 2, wherein a plurality of electrode pads to which the bump electrodes for input/output power supply are connected are formed on a surface of the wiring substrate, and a power supply plane connected electrically to the electrode pads via through holes is formed in the interior of the wiring substrate, the through holes being arranged in an area opposed to the third area of the semiconductor chip.

4. A semiconductor device according to claim 1, wherein the metal wirings and the bump electrodes are formed in a wafer process.

5. A semiconductor device according to claim 1, wherein memory cells of SRAM are formed in an area other than the central area of the main surface of the semiconductor chip.

6. A semiconductor device according to claim 1, wherein the metal wirings are formed of copper film as a principal component.

7. A semiconductor device according to claim 1, wherein the bump electrodes are formed of a solder material which comprises tin as a principal component.

8. A semiconductor device according to claim 1, wherein a metallic cover plate is affixed to a back surface of the semiconductor chip using an adhesive.

9. A semiconductor device in which a semiconductor chip is flip-chip-mounted over a wiring substrate through a plurality of bump electrodes formed over a main surface of the semiconductor chip,

wherein the main surface of the semiconductor chip has a first area, a second area and a third area,

wherein an input/output circuit is arranged in the first area of the main surface of the semiconductor chip,

wherein the plurality of bump electrodes are arrayed on the main surface of the semiconductor chip,

wherein a gap between the semiconductor chip and the wiring substrate is filled with a sealing resin,

wherein the plurality of bump electrodes include first bump electrodes arrayed with a first gap therebetween and second bump electrodes arrayed with a second gap therebetween,

wherein the first bump electrodes are connected by metal wirings with the input/output circuits, and are arranged in the second area of the main surface of the semiconductor chip,

wherein the second hump electrodes are arrayed in the third area,

wherein the first gap is less than the second gap,

wherein the second area is located between the first area and the third area, and

wherein the third area is located between the second area and a side of the main surface of the semiconductor chip.

10. A semiconductor device according to claim 9, wherein the first area is a central area of the main surface of the semiconductor chip.

11. A semiconductor device according to claim 9, wherein lands integral with the metal wirings and to which the bump electrodes are not connected are arrayed in the second area.

12. A semiconductor device according to claim 9, wherein the plurality of bump electrodes include bump electrodes functionally connected to an input/output power supply, an input and output of a data signal, and an input of an address signal,

wherein, of the first bump electrode in the plurality of bump electrodes, those for the input/output power supply and those for the input and output of a data signal are mainly arranged in the first area, and

wherein, of the second bump electrodes in the plurality of bump electrodes, chose for the input of an address signal are mainly arrayed in the second area.

13. A semiconductor device according to claim 9, wherein a plurality of electrode pads to which the plurality of bump electrodes for an input/output power supply are connected are formed on a surface of the wiring substrate, and a power supply plane connected electrically to the electrode pads via through holes is formed in the interior of the wiring substrate, the through holes being arranged in an area opposed to the third area of the semiconductor chip.

14. A semiconductor device according to claim 9, wherein the metal wirings and the plurality of bump electrodes are formed in a wafer process.

15. A semiconductor device according to claim 9, wherein memory cells of SRAM are formed in an area other then the first area of the main surface of the semiconductor chip.

16. A semiconductor device according to claim 9, wherein the metal wirings are formed of copper film as a principal component.

17. A semiconductor device according to claim 9, wherein the bump electrodes are formed of a solder material which comprises tin as a principal component.

18. A semiconductor device according to claim 9, wherein a power supply circuit and a plurality of pads are arranged in the first area of the main surface of the semiconductor chip, and

wherein the plurality of bump electrodes are electrically connected to the pads through the metal wirings.