System and methods for manufacturing non-volatile semiconductor memory apparatus

• US 6,868,012 B2
• Filed: 09/19/2002
• Issued: 03/15/2005
• Est. Priority Date: 09/19/2001
• Status: Expired due to Fees

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Natori, Kanji
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US10/246,708
• Publication Number:
  US 20030095443A1
• Time in Patent Office: 908 Days
• Field of Search: 365/185.18, 365/185.03, 365/189.07, 365/226, 327/536, 327/537
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The invention provides a non-volatile semiconductor that prevents an output from a charge pump from lowering below an operation voltage even in a read operation, and reduces the capacity of a pool capacitor to thereby reduce the size of the apparatus. The invention can include a strong charge pump that generates 5.0V and a power supply voltage of 8.0V. The power supply voltage is supplied to constant voltage circuits. The constant voltage circuits generate voltages corresponding to the respective read, program and erase operation modes. The operation voltage required at the time of programming is 8.0V. In contrast, the operation voltage required at the time of reading is 3.0V. In other words, the charge pump outputs a voltage sufficiently higher than the operation voltage at the time of reading. With this, the output of the charge pump has a margin, such that, an output greater than the operation voltage can always be secured even when the output lowers through setting of the operation voltages. Accordingly, the capacity of the charge capacitor that pools the output of the charge pump can be reduced, and thus the apparatus can be reduced in size.

Claims

1. A non-volatile semiconductor memory apparatus, comprising:

an operation voltage setting device that sets an operation voltage for executing each of reading, programming and erasing operations for a specified non-volatile memory element within a memory array composed of a plurality of non-volatile memory elements;

a constant voltage device that is provided with a stepped up power supply voltage and that generates a constant voltage that is identical to the operation voltage; and

a charge pump device that steps up and supplies the power supply voltage to the constant voltage device, and that sets the power supply voltage supplied to the constant voltage device higher than the operation voltage by an amount of voltage drop that is generated through setting the operation voltage for the non-volatile memory.

2. The non-volatile semiconductor memory apparatus according to claim 1, the non-volatile memory element including an ONO film composed of an oxide film (O), a nitride film (N) and an oxide film (O) as a charge trap site.

3. The non-volatile semiconductor memory apparatus according to claim 1, the charge pump device stepping up the power supply voltage to generate a plurality of voltages.

4. The non-volatile semiconductor memory apparatus according to claim 1, the constant voltage device being capable of generating constant voltages of different voltage values according to at least one of a read mode, program mode and erase mode for the non-volatile memory element.

5. The non-volatile semiconductor memory apparatus according to claim 1, the non-volatile memory element being a memory element that includes a twin memory cell controlled by one word gate and first and second control gates.

6. The non-volatile semiconductor memory apparatus according to claim 5, the operation voltage setting device setting voltage values provided from the constant voltage device independently for the first and second control gates, and an impurity layer that accesses trapped charge of the non-volatile memory element.

7. The non-volatile semiconductor memory apparatus according to claim 5, the operation voltage setting device, comprising:

a word line that is connected to a word gate of the twin memory cell in a same row;

a control gate line that is commonly connected to mutually adjacent first and second control gates in a same column of the twin memory cells arranged adjacent to each other in a row direction; and

a bit line that is commonly connected to impurity layers that access trapped charge arranged in the same column of the mutually adjacent non-volatile memory elements of the twin memory cells arranged adjacent to each other in the row direction,

wherein voltage values provided from the constant voltage device are set independently for the control gate line and the bit line.

8. The non-volatile semiconductor memory apparatus according to claim 1, further comprising a pool capacitor that pools an output of the charge pump device.

9. A non-volatile semiconductor memory apparatus, comprising:

an operation voltage setting device that sets an operation voltage for executing each of reading, programming and erasing operations for a specified non-volatile memory element within a memory array including a plurality of twin memory cells, each of the twin memory cells having two non-volatile memory elements controlled by one word gate, and first and second control gates;

a constant voltage device that is provided with a stepped up power supply voltage and that generates a constant voltage identical with the operation voltage; and

a charge pump device that steps up and supplies the power supply voltage to the constant voltage device, generates a voltage with a greater margin for the operating voltage to be supplied to the first and second control gates in a reading mode than in other modes, and supplies the voltage to the constant voltage device as a power supply voltage.

10. The non-volatile semiconductor memory apparatus according to claim 9, further comprising a pool capacitor that pools an output of the charge pump device.

11. The non-volatile semiconductor memory apparatus according to claim 9, the non-volatile memory element including an ONO film composed of an oxide film (O), a nitride film (N) and an oxide film (O) as a charge trap site.

12. A non-volatile semiconductor memory apparatus, comprising:

an operation voltage setting device that sets an operation voltage for executing each of reading, programming and erasing operations for a specified non-volatile memory element within a memory array composed of a plurality of non-volatile memory elements;

a constant voltage device that is provided with a stepped up power supply voltage and that generates a constant voltage that is identical with the operation voltage; and

a charge pump device that steps up and supplies the power supply voltage to the constant voltage device, generates a voltage with a greater margin for the operating voltage in a reading mode for the non-volatile memory element than in other modes, and that supplies the voltage to the constant voltage device as a power supply voltage.

13. The non-volatile semiconductor memory apparatus according to claim 12, the non-volatile memory element being a memory element that includes a twin memory cell controlled by one word gate and first and second control gates.

14. The non-volatile semiconductor memory apparatus according to claim 12, further comprising a pool capacitor that pools an output of the charge pump device.

15. The non-volatile semiconductor memory apparatus according to claim 12, the charge pump device stepping up the power supply voltage to generate a plurality of voltages.

16. The non-volatile semiconductor memory apparatus according to claim 12, the non-volatile memory element including an ONO film composed of an oxide film (O), a nitride film (N) and an oxide film (O) as a charge trap site.

17. The non-volatile semiconductor memory apparatus according to claim 12, the constant voltage device being capable of generating constant voltages of different voltage values according to at last one of a read mode, program mode and erase mode for the non-volatile memory element.