Semiconductor memory device, and method of controlling the same

• US 6,868,026 B2
• Filed: 02/13/2003
• Issued: 03/15/2005
• Est. Priority Date: 11/09/1999
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Fujioka, Shinya
• Primary Examiner(s): Yoha, Connie C.
• Application Number:
  US10/365,456
• Publication Number:
  US 20030227810A1
• Time in Patent Office: 761 Days
• Field of Search: 365/222, 365/149, 365/226, 365/233
• US Class Current: 365/222
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2211/4067 Refresh in standby or low power modes
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Claims

1. A semiconductor memory device comprising:

a self-refresh control circuit for automatically refreshing memory cells at a predetermined cycle; and

an internal voltage generator for generating an internal voltage to be supplied to a predetermined internal circuit, upon receipt of a power supply voltage from an exterior, and wherein

said self-refresh control circuit is inactivated in order to disable a refresh operation, and supply capacity of said internal voltage in said internal voltage generator is lowered when a control signal is received from the exterior, thereby entering the device into a low power consumption mode which does not execute the refresh operation.

2. A semiconductor memory device according to claim 1,

wherein said internal voltage generator includes plurality of units for generating said internal voltage;

and

a part of said units suspend(s) during said low power consumption mode.

3. A semiconductor memory device comprising:

a self-refresh control circuit for automatically refreshing memory cells, including a timer for determining a length of a refresh cycle, and wherein

said self-refresh control circuit is inactivated in order to disable a refresh operation by suspending an operation of the timer in response to an external control signal, to enter a low power consumption mode which does not execute the refresh operation.

4. A method of controlling a semiconductor memory device comprising:

a self-refresh control circuit for automatically refreshing memory cells at a predetermined cycle; and

an internal voltage generator for generating an internal voltage to be supplied to a predetermined internal circuit upon receipt of a power supply voltage from an exterior, further comprising the steps of;

inactivating said self-refresh control circuit in order to disable a refresh operation and lowering supply capability of said internal voltage in said internal voltage generator when a control signal is received from the exterior; and

entering the device into a low power consumption mode which does not execute the refresh operation.

5. A method of controlling a semiconductor memory device comprising a self-refresh control circuit for automatically refreshing memory cells, that includes a timer for determining a length of a refresh cycle, further comprising the steps of:

inactivating said self-refresh control circuit in order to disable a refresh operation by suspending an operation of the timer in response to an external control signal; and

entering a low power consumption mode which does not execute the refresh operation in which refresh operation of the memory cells is not performed.