Network device with embedded timing synchronization
First Claim
1. A network device, comprising:
- a central timing subsystem providing a timing reference signal comprising a main timing signal and an embedded timing signal comprises;
an embeddor circuit for distorting the duty cycle of the main timing signal to encode the embedded timing signal within the main timing signal to provide the timing reference signal, wherein the embeddor circuit comprises;
a plurality of cascaded registers for providing the timing reference signal;
a rollover counter for counting to a predetermined number corresponding to a clock period of the embedded timing signal; and
a load circuit for loading a predetermined value into the plurality of cascaded registers when the rollover counter rolls over to distort the duty cycle of the main timing reference signal.
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Accused Products
Abstract
The present invention provides a network device including a central timing subsystem for distributing one or more timing reference signals including a main timing signal and an embedded timing signal. Embedding one timing signal within another reduces the routing resources necessary to route the timing signal(s) within the network device. In addition, one central timing system, as opposed to two or more, may be used to provide multiple different synchronous clock signals. In one embodiment, the main timing signal is used for network data transfer while the embedded signal is used at least for processor synchronization. Consequently, a separate central timing subsystem is not required for generation and distribution of processor timing reference signals, and separate routing resources are not required for the processor timing reference signals. In addition, separate local timing subsystems for both the central timing and processor timing are not necessary. Embedding the processor timing reference signal within a highly accurate, redundant external timing reference signal also provides a highly accurate and redundant processor timing reference signal, and having a common local timing subsystem is more efficient resulting in less design time, less debug time, less risk, design re-use and simulation re-use.
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Citations
28 Claims
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1. A network device, comprising:
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a central timing subsystem providing a timing reference signal comprising a main timing signal and an embedded timing signal comprises;
an embeddor circuit for distorting the duty cycle of the main timing signal to encode the embedded timing signal within the main timing signal to provide the timing reference signal, wherein the embeddor circuit comprises;
a plurality of cascaded registers for providing the timing reference signal;
a rollover counter for counting to a predetermined number corresponding to a clock period of the embedded timing signal; and
a load circuit for loading a predetermined value into the plurality of cascaded registers when the rollover counter rolls over to distort the duty cycle of the main timing reference signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A network device, comprising:
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a first central timing subsystem providing a first timing reference signal and a first master control signal;
a second central timing subsystem providing a second timing reference signal and a second master control signal;
wherein the first central timing subsystem receives the second timing reference signal and the second master control signal and the second central timing subsystem receives the first timing reference signal and the first master control signal;
wherein the first central timing subsystem synchronizes the first timing reference signal to the second timing reference signal in accordance with the second master control signal and the second central timing subsystem synchronizes the second timing reference signal to the first timing reference signal in accordance with the first master control signal;
wherein the first timing reference signal comprises a first main timing signal and a first embedded timing signal. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 21)
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19. A method of operating a network device, comprising:
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providing a timing reference signal comprising a main timing signal and an embeded timing signal from a central timing subsystem;
distorting the duty cycle of the main timing reference signal to provide the embedded timing reference signal; and
detecting the distorted duty cycle at a local timing subsystem.
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22. A method of operating a network device, comprising:
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providing a first timing reference signal including a first main timing reference signal and a first embedded timing reference signal from a first central timing subsystem;
providing a first master control signal from the first central timing subsystem;
providing a second timing reference signal including a second main timing reference and a second embedded timing reference signal from a second central timing subsystem;
providing a second master control signal from the second central timing subsystem;
synchronizing the second timing reference signal to the first timing reference signal in accordance with the first master control signal; and
synchronizing the first timing reference signal to the second timing reference signal in accordance with the second master control signal. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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Specification