Network device with embedded timing synchronization

• US 6,868,092 B1
• Filed: 07/11/2000
• Issued: 03/15/2005
• Est. Priority Date: 05/20/2000
• Status: Expired due to Term

• Current Assignee: Ciena Corporation
• Original Assignee: Ciena Corporation
• Inventors: Bell, Colin, Branscomb, Brian
• Primary Examiner(s): HO, DUC CHI
• Application Number:
  US09/613,682
• Time in Patent Office: 1,708 Days
• Field of Search: 370/503, 370/590, 370/401, 709248-250, 714/798, 714/25, 713/400, 713/500, 713/501, 327/141, 327/175, 327/35, 375/356
• US Class Current: 370/503
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 41/0803 Configuration setting
• CPC Class Codes: H04L 41/085 Retrieval of network configuration; Tracking network configuration history
• CPC Class Codes: H04L 41/22 comprising specially adapted graphical user interfaces [GUI]
• CPC Class Codes: H04L 45/50 using label swapping, e.g. multi-protocol label switch [MPLS]
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

The present invention provides a network device including a central timing subsystem for distributing one or more timing reference signals including a main timing signal and an embedded timing signal. Embedding one timing signal within another reduces the routing resources necessary to route the timing signal(s) within the network device. In addition, one central timing system, as opposed to two or more, may be used to provide multiple different synchronous clock signals. In one embodiment, the main timing signal is used for network data transfer while the embedded signal is used at least for processor synchronization. Consequently, a separate central timing subsystem is not required for generation and distribution of processor timing reference signals, and separate routing resources are not required for the processor timing reference signals. In addition, separate local timing subsystems for both the central timing and processor timing are not necessary. Embedding the processor timing reference signal within a highly accurate, redundant external timing reference signal also provides a highly accurate and redundant processor timing reference signal, and having a common local timing subsystem is more efficient resulting in less design time, less debug time, less risk, design re-use and simulation re-use.

Claims

1. A network device, comprising:

a central timing subsystem providing a timing reference signal comprising a main timing signal and an embedded timing signal comprises;

an embeddor circuit for distorting the duty cycle of the main timing signal to encode the embedded timing signal within the main timing signal to provide the timing reference signal, wherein the embeddor circuit comprises;

a plurality of cascaded registers for providing the timing reference signal;

a rollover counter for counting to a predetermined number corresponding to a clock period of the embedded timing signal; and

a load circuit for loading a predetermined value into the plurality of cascaded registers when the rollover counter rolls over to distort the duty cycle of the main timing reference signal.

2. The network device of claim 1, wherein the plurality of cascaded registers comprises:

a first register coupled with the load circuit;

a second register coupled with the load circuit and coupled to the first register for receiving an output of the first register;

an inverter coupled to the second register for inverting an output of the second register and providing an input to the first register;

a third register coupled with the load circuit and coupled to the second register for receiving the output of the second register; and

a fourth register coupled with the load circuit and coupled to the third register for receiving the output of the third register and for providing the timing reference signal.

3. The network device of claim 1, wherein the central timing subsystem further comprises:

an extractor circuit for detecting the distorted duty cycle of the main timing signal and for generating an extracted timing signal.

4. The network device of claim 3, wherein the network device further comprises:

a BITS T1/E1 framer for receiving the extracted timing signal.

5. The network device of claim 1, wherein the network device further comprises:

a local timing subsystem coupled to the timing reference signal for synchronizing a local main timing signal to the main timing reference signal within the timing reference signal.

6. The network device of claim 1, wherein the network device further comprises:

a local timing subsystem coupled to the timing reference signal for extracting a local timing signal corresponding to the embedded timing signal.

7. The network device of claim 6, wherein the network device further comprises:

a processor for receiving the local timing signal.

8. The network device of claim 6, wherein the network device further comprises:

a data transfer subsystem for receiving the local timing signal.

9. A network device, comprising:

a first central timing subsystem providing a first timing reference signal and a first master control signal;

a second central timing subsystem providing a second timing reference signal and a second master control signal;

wherein the first central timing subsystem receives the second timing reference signal and the second master control signal and the second central timing subsystem receives the first timing reference signal and the first master control signal;

wherein the first central timing subsystem synchronizes the first timing reference signal to the second timing reference signal in accordance with the second master control signal and the second central timing subsystem synchronizes the second timing reference signal to the first timing reference signal in accordance with the first master control signal;

wherein the first timing reference signal comprises a first main timing signal and a first embedded timing signal.

10. The network device of claim 9, wherein the second timing reference signal comprises a second main timing signal and a second embedded timing signal.

11. The network device of claim 10, wherein the network device further comprises:

a local timing subsystem coupled to the first timing reference signal and the second timing reference signal for synchronizing a local main timing signal to one of the first main timing signal within the first timing reference signal and the second main timing signal within the second timing reference signal.

12. The network device of claim 10, wherein the network device further comprises:

a local timing subsystem coupled to the first timing reference signal and the second timing reference signal for extracting a local timing signal corresponding to one of the first embedded timing signal and the second embedded timing signal.

13. The network device of claim 12, wherein the network device further comprises:

a processor for receiving the local timing signal.

14. The network device of claim 12, wherein the network device further comprises:

a data transfer subsystem for receiving the local timing signal.

15. The network device of claim 9, wherein the first central timing subsystem comprises:

an embeddor circuit for distorting the duty cycle of the first main timing signal to encode the first embedded timing signal within the first main timing signal to provide the first timing reference signal.

16. The network device of claim 13, wherein the embeddor circuit comprises:

a plurality of cascaded registers for providing the first timing reference signal;

a rollover counter for counting to a predetermined number corresponding to a clock period of the first embedded timing signal; and

a load circuit for loading a predetermined value into the plurality of cascaded registers when the rollover counter rolls over to distort the duty cycle of the first main timing reference signal.

17. The network device of claim 15, wherein the first central timing subsystem further comprises:

an extractor circuit for detecting the distorted duty cycle of the first main timing signal and for generating an extracted timing signal.

18. The network device of claim 17, wherein the network device further comprises:

a BITS T1/E1 framer for receiving the extracted timing signal.

20. The method of claim 14, further comprising:

providing a local timing signal to a processor.

21. The method of claim 14, further comprising:

providing a local timing signal to a data transfer subsystem.

19. A method of operating a network device, comprising:

providing a timing reference signal comprising a main timing signal and an embeded timing signal from a central timing subsystem;

distorting the duty cycle of the main timing reference signal to provide the embedded timing reference signal; and

detecting the distorted duty cycle at a local timing subsystem.

22. A method of operating a network device, comprising:

providing a first timing reference signal including a first main timing reference signal and a first embedded timing reference signal from a first central timing subsystem;

providing a first master control signal from the first central timing subsystem;

providing a second timing reference signal including a second main timing reference and a second embedded timing reference signal from a second central timing subsystem;

providing a second master control signal from the second central timing subsystem;

synchronizing the second timing reference signal to the first timing reference signal in accordance with the first master control signal; and

synchronizing the first timing reference signal to the second timing reference signal in accordance with the second master control signal.

23. The method of claim 22, further comprising:

distorting the duty cycle of the first main timing reference signal to encode the first embedded timing reference signal within the first main timing reference signal and provide the first timing reference signal.

24. The method of claim 23, further comprising:

detecting the distorted duty cycle at a local timing subsystem.

25. The method of claim 24, further comprising:

providing a local timing signal to a processor.

26. The method of claim 24, further comprising:

providing a local timing signal to a data transfer subsystem.

27. The method of claim 22, further comprising:

extracting the second embedded timing reference signal from the second timing reference signal within the first central timing subsystem when the first timing reference signal is synchronized to the second timing reference signal.

28. The method of claim 22, further comprising:

extracting the first embedded timing reference signal from the first timing reference signal within the second central timing subsystem when the second timing reference signal is synchronized to the first timing reference signal.