Method for validating write data to a memory

• US 6,868,516 B1
• Filed: 12/21/2000
• Issued: 03/15/2005
• Est. Priority Date: 12/21/2000
• Status: Expired due to Term

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: MacLellan, Christopher S., Walton, John K.
• Primary Examiner(s): Chung, Phung M.
• Application Number:
  US09/746,496
• Time in Patent Office: 1,545 Days
• Field of Search: 714/763, 714/703, 714/776, 714/758, 714/801, 714/800, 714/823, 714/819, 714/785, 714/746
• US Class Current: 714/758
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00

Abstract

A method and system for checking the Cyclic Redundancy Cycle (CRC) of DATA, such DATA comprising a series of data words terminating in a CRC portion. The method includes: checking the CRC of the data words while delaying the DATA from passing to an output; and corrupting the delayed DATA if such checking determines a CRC error, such corruption of the DATA being performed prior to the data words pass to said output. The corrupting comprises corrupting a parity byte of such data words.

Claims

1. A method for checking the Cyclic Redundancy Check(CRC) of DATA, such DATA comprising a series of data words terminating in a CRC portion, such method comprising:

checking the CRC of the data words while delaying the DATA from passing to an output, each data word in the series being associated with a clock pulse, such delay comprising a plurality of clock pulses;

corrupting the delayed DATA if such checking determines a CRC error, such corruption of the DATA being performed prior to the data words passes to said output; and

checking the output to determine whether there has been a corruption of the delayed DATA.

2. A method for checking the Cyclic Redundancy Check (CRC) of DATA, such DATA comprising a series of data words terminating in a CRC portion, such method comprising:

checking the CRC of the data words while delaying the DATA from passing to an output, each data word in the series being associated with a clock pulse, such delay comprising a plurality of clock pulses;

corrupting the delayed DATA if such checking determines a CRC error, such corruption of the DATA being performed prior to the data words pass to said output;

checking the output to determine whether there has been a corruption of the delayed DATA; and

wherein the corrupting comprising corrupting a parity bit of one such data words.

3. A system, comprising;

a source of DATA, such DATA comprising a series of bytes each byte having a parity bit, such series of bytes terminating in a Cyclic Redundancy Check (CRC) portion associated with the series of bytes of the DATA,

a source of a the CRC portion;

a CRC checker fed by the series of bytes of the DATA and the source of the CRC portion, for determining a CRC from the seines series of bytes and for comparing such determined CRC with the CRC fed by the CRC source;

a delay fed by the series of bytes and the parity bits thereof, a selector having a first input thereof fed by the parity bits and a second input thereof fed by the complement of such parity bits, such selector coupling the first input thereof to an output of such selector when the determined CRC is the same as the CRC fed by the CRC source and for coupling the second input thereof to the output when the determined CRC is different from the CRC fed by the CRC source, the output of the selector providing an appended parity bit for the data bytes after such data bytes pass through the delay.

4. A system, comprising;

a source of DATA, such DATA comprising a series of data words, each data word having a parity bit, each data word in the series being associated with a clock pulse, such series of data words terminating in a Cyclic Redundancy Check (CRC) portion associated with the series of bytes of the DATA, such CRC portion comprising a predetermined number of CRC words, each one of such CRC words being associated with one of the clock pulses;

a source of a the CRC portion;

a CRC checker fed by the series of data words and the source of the CRC portion, for determining a CRC from the series of data words and for comparing such determined CRC with the CRC fed by the CRC source;

a delay fed by the series of DATA, such delay delaying the DATA by at least the number of CRC words;

a selector having a first input thereof fed by the parity bits and a second input thereof fed by the complement of such parity bits, such selector coupling the first input thereof to an output of such selector when the determined CRC is the same as the CRC fed by the CRC source and for coupling the second input thereof to the output when the determined CRC is different from the CRC source, the output of the selector providing an appended parity bit for the data words after such DATA has passed through the delay.

5. The system recited in claim 4 including a second selector, such second selector having a first input fed the DATA and a second input fed by the output of the first-mentioned selector, such second selector coupling either the first input thereof or the second input thereof to an output of the second selector selectively in accordance with a control signal fed to such second selector.