Hybrid thin film/thick film solid oxide fuel cell and method of manufacturing the same

• US 6,869,722 B2
• Filed: 10/31/2003
• Issued: 03/22/2005
• Est. Priority Date: 04/19/2001
• Status: Expired due to Fees

• Current Assignee: Intelligent Energy Limited (Lb-shell Plc)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Kearl, Daniel A.
• Primary Examiner(s): DOVE, TRACY MAE
• Application Number:
  US10/698,136
• Publication Number:
  US 20040091609A1
• Time in Patent Office: 508 Days
• Field of Search: 429/30, 429 32- 34, 429 40- 42, 429/44, 296/231
• US Class Current: 429/535
• CPC Class Codes: H01M 16/006 of fuel cells with rechargeable batteries
• CPC Class Codes: H01M 2008/1293 Fuel cells with solid oxide electrolytes
• CPC Class Codes: H01M 2250/30 Fuel cells in portable systems, e.g. mobile phone, laptop
• CPC Class Codes: H01M 4/861 with a gradient in the porosity
• CPC Class Codes: H01M 4/8621 containing only metallic or ceramic material, e.g. made by sintering or sputtering
• CPC Class Codes: H01M 4/8885 Sintering or firing
• CPC Class Codes: H01M 4/9033 Complex oxides, optionally doped, of the type M1MeO3, M1 being an alkaline earth metal or a rare earth, Me being a metal, e.g. perovskites
• CPC Class Codes: H01M 4/9066 of metal-ceramic composites or mixtures, e.g. cermets
• CPC Class Codes: H01M 8/0204 Non-porous and characterised by the material
• CPC Class Codes: H01M 8/1213 characterised by the electrode/electrolyte combination or the supporting material
• CPC Class Codes: H01M 8/1226 characterised by the supporting layer
• CPC Class Codes: H01M 8/1246 the electrolyte consisting of oxides
• CPC Class Codes: H01M 8/1286 Fuel cells applied on a support, e.g. miniature fuel cells deposited on silica supports
• CPC Class Codes: H01M 8/2428 Grouping by arranging unit cells on a surface of any form, e.g. planar or tubular
• CPC Class Codes: H01M 8/2432 Grouping of unit cells of planar configuration
• CPC Class Codes: Y02B 90/10 Applications of fuel cells in buildings
• CPC Class Codes: Y02E 60/10 Energy storage using batteries
• CPC Class Codes: Y02E 60/50 Fuel cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10T 29/49108 Electric battery cell making

Abstract

A SOFC providing higher power densities than PEM-based cells; the possibility of direct oxidation and/or internal reforming of fuel; and reduced SOFC operating temperatures. The SOFC comprises a thin film electrolyte layer. A thick film anode layer is disposed on one surface of the electrolyte layer; and a thick film cathode layer is disposed on the opposite surface of the electrolyte layer. A method of making the SOFC comprises the steps of: creating a well in one side of a dielectric or semiconductor substrate; depositing a thin film solid oxide electrolyte layer on the surface of the well; applying a thick film electrode layer in the electrolyte coated well; creating a counter well in the opposite side of the substrate, the counter well abutting the electrolyte layer; and applying a thick film counter electrode layer in the counter well.

Claims

1. A method of making a fuel cell, the method comprising the steps of:

creating a well in a dielectric or semiconductor substrate, the substrate having a first side and a second side, the second side opposed to the first side, and the well being defined in the first side;

depositing a thin film solid oxide electrolyte layer on a surface of the well;

applying an electrode layer in the electrolyte coated well;

creating a counter well in the second side, the counter well abutting the electrolyte layer; and

applying a counter electrode layer in the counter well.

2. The method as defined in claim 1 wherein the step of depositing the electrolyte layer is performed by at least one of sputter deposition or chemical vapor deposition (CVD).

3. The method as defined in claim 1, further comprising the step of firing the electrolyte layer prior to application of the electrode layer.

4. The method as defined in claim 1, further comprising the step of applying an isolation dielectric on the second side of the substrate.

5. The method as defined in claim 4 wherein the substrate is silicon, and wherein the isolation dielectric is grown on the second side of the substrate.

6. The method as defined in claim 1, further comprising the step of processing the electrode layer and the counter electrode layer using planarization techniques.

7. The method as defined in claim 6 wherein the planarization is performed by at least one of chemical mechanical polishing (CMP) or mechanical polishing.

8. The method as defined in claim 1, further comprising the step of applying a hard mask to the first side of the substrate before the step of creating a well.

9. The method as defined in claim 8 wherein the substrate is silicon, and wherein the first side hard mask is grown on the substrate first side.

10. The method as defined in claim 1, further comprising the step of applying a hard mask to the second side of the substrate before the step of creating a counter well.

11. The method as defined in claim 10 wherein the substrate is silicon, and wherein the second side hard mask is grown on the substrate second side.

12. The method as defined in claim 1 wherein the step of creating the well and the step of creating the counter well are each carried out by etching.

13. The method as defined in claim 12 wherein the substrate is silicon, and wherein the etching is performed by an etchant selected from the group consisting of wet anisotropic etchants, plasma anisotropic etchants, and mixtures thereof, thereby forming ultra-smooth surfaces on the well and the counter well.

14. The method as defined in claim 13 wherein the wet anisotropic etchants are selected from the group consisting of potassium hydroxide (KOH), tetramethyl ammonium hydroxide (TMAH), a mixture of potassium hydroxide and isopropyl alcohol, ammonium hydroxide, sodium hydroxide, cerium hydroxide, ethylene diamine pyrocatechol, and mixtures thereof.

15. The method as defined in claim 13 wherein the plasma anisotropic etchant is sulfur hexafluoride alternated with C₄F₈.

16. The method as defined in claim 12 wherein the substrate is a silicon oxide containing dielectric substrate, and wherein the etching is performed by a hydrofluoric containing isotropic etchant.

17. The method as defined in claim 1 wherein the substrate is selected from the group consisting of single crystalline silicon, polycrystalline silicon, silicon oxide containing dielectric substrate, alumina, sapphire, ceramic, and mixtures thereof.

18. The method as defined in claim 17 wherein the substrate is single crystalline silicon.

19. The method as defined in claim 1 wherein at least one of the electrode layer contained in the well or counter electrode layer contained in the counter well is a thick film electrode layer.

20. The method as defined in claim 19 wherein the electrode layer contained in the well is a thick film electrode layer and the counter electrode layer contained in the counter well is a thick film counter electrode layer.

21. A method of making a fuel cell, the method comprising the steps of:

creating a well in a dielectric or semiconductor substrate, the substrate having a first side and a second side, the second side opposed to the first side, and the well being defined in the first side;

depositing a thin film solid oxide electrolyte layer on a surface of the well, wherein the step of depositing the electrolyte layer is performed by at least one of sputter deposition or chemical vapor deposition (CVD);

applying an electrode layer in the electrolyte coated well;

creating a counter well in the second side, the counter well abutting the electrolyte layer, wherein the step of creating the well and the step of creating the counter well are each carried out by etching;

applying an isolation dielectric on the second side of the substrate;

applying a counter electrode layer in the counter well; and

processing the electrode layer and the counter electrode layer using planarization techniques, wherein the planarization is performed by at least one of chemical mechanical polishing (CMP) or mechanical polishing.

22. The method as defined in claim 21, further comprising the step of firing the electrolyte layer prior to application of the electrode layer.

23. The method as defined in claim 21 wherein the substrate is silicon, and wherein the isolation dielectric is grown on the second side of the substrate.

24. The method as defined in claim 21, further comprising the step of applying a hard mask to the first side of the substrate before the step of creating a well.

25. The method as defined in claim 24 wherein the substrate is silicon, and wherein the first side hard mask is grown on the substrate first side.

26. The method as defined in claim 21, further comprising the step of applying a hard mask to the second side of the substrate before the step of creating a counter well.

27. The method as defined in claim 26 wherein the substrate is silicon, and wherein the second side hard mask is grown on the substrate second side.

28. The method as defined in claim 21 wherein the substrate is silicon, and wherein the etching is performed by an etchant selected from the group consisting of wet anisotropic etchants, plasma anisotropic etchants, and mixtures thereof, thereby forming ultra-smooth surfaces on the well and the counter well.

29. The method as defined in claim 28 wherein the wet anisotropic etchants are selected from the group consisting of potassium hydroxide (KOH), tetramethyl ammonium hydroxide (TMAH), a mixture of potassium hydroxide and isopropyl alcohol, ammonium hydroxide, sodium hydroxide, cerium hydroxide, ethylene diamine pyrocatechol, and mixtures thereof.

30. The method as defined in claim 28 wherein the plasma anisotropic etchant is sulfur hexafluoride alternated with C₄F₈.

31. The method as defined in claim 21 wherein the substrate is a silicon oxide containing dielectric substrate, and wherein the etching is performed by a hydrofluoric containing isotropic etchant.

32. The method as defined in claim 21 wherein the substrate is selected from the group consisting of single crystalline silicon, polycrystalline silicon, silicon oxide containing dielectric substrate, alumina, sapphire, ceramic, and mixtures thereof.

33. The method as defined in claim 32 wherein the substrate is single crystalline silicon.

34. The method as defined in claim 21 wherein at least one of the electrode layer contained in the well or counter electrode layer contained in the counter well is a thick film electrode layer.

35. The method as defined in claim 34 wherein the electrode layer contained in the well is a thick film electrode layer and the counter electrode layer contained in the counter well is a thick film counter electrode layer.