Image sensor and method of manufacturing the same

• US 6,869,817 B2
• Filed: 08/30/2002
• Issued: 03/22/2005
• Est. Priority Date: 11/16/2001
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Hwang, Joon
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US10/233,143
• Publication Number:
  US 20030096443A1
• Time in Patent Office: 935 Days
• Field of Search: 438/48, 438/59, 438 66- 99, 438303-307
• US Class Current: 438/48
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

Disclosed is a method of manufacturing an image sensor having light sensitivity over a photodiode equal in area to that of a unit pixel. The image sensor includes an image sensor comprising: a first semiconductor substrate doped with a first conductive dopant; a first diffusion layer formed in the semiconductor substrate and doped with a second conductive dopant; a second diffusion layer formed in the semiconductor substrate adjacent the first diffusion layer and having a width wider than a width of the first diffusion layer; a third diffusion layer doped with the first conductive dopant and formed at an exposed surface of the semiconductor substrate in the first diffusion layer; a gate electrode formed on the exposed surface and having a first edge adjacent to the third diffusion layer; and a fourth diffusion layer doped with the second conductive dopant and formed at the exposed surface adjacent a second edge of the gate electrode, the fourth diffusion layer defining a gap with the second diffusion layer.

Claims

1. A method of manufacturing an image sensor, comprising the steps of:

a) forming a first diffusion layer within a semiconductor substrate, semiconductor substrate being doped of a first conductive dopant and the first diffusion layer being doped of a second conductive dopant;

b) forming a gate electrode on the semiconductor substrate, the gate electrode having a first sidewall and a second sidewall;

c) forming a second diffusion layer in the semiconductor substrate adjacent the first diffusion layer;

d) forming a first spacer at the first sidewall and a second spacer at the second sidewall;

e) forming a third diffusion layer in the second diffusion layer adjacent the first spacer, the third diffusion layer being doped with the first conductive dopant; and

f) forming a fourth diffusion layer within the semiconductor substrate adjacent the second spacer, the fourth diffusion layer being doped with the second conductive dopant,

wherein a part of the first diffusion layer is under the fourth diffusion layer.

2. The method of claim 1, wherein a dopant concentration of the first diffusion layer is equal to a dopant concentration in the second diffusion layer, a dopant concentration of the third diffusion layer is higher than the dopant concentration of the first diffusion layer and a dopant concentration of the fourth diffusion layer is higher than the dopant concentration of the second diffusion layer.

3. The method of claim 1, wherein an ion injection energy for forming the first diffusion layer is larger than an ion injection energy for forming the second diffusion layer and an ion injection energy for forming the third diffusion layer is smaller than an ion injection energy for forming the second diffusion layer.

4. The method of claim 1, wherein the first diffusion layer and the fourth diffusion layer define a gap for preventing a short when the first diffusion layer and the second diffusion layer are depleted.

5. A method of manufacturing an image sensor, comprising the steps of:

a) forming a first diffusion layer within a semiconductor substrate, the semiconductor substrate being doped of a first conductive dopant and the first diffusion layer being doped of a second conductive dopant;

b) forming a gate electrode on the semiconductor substrate, the gate electrode having a first sidewall and a second sidewall;

c) forming a second diffusion layer in the semiconductor substrate adjacent the first diffusion layer;

d) forming a first spacer at the first sidewall and a second spacer at the second sidewall;

e) forming a third diffusion layer in the second diffusion layer adjacent the first spacer, the third diffusion layer being doped with the first conductive dopant;

f) forming a fourth diffusion layer within the semiconductor substrate adjacent the second spacer, the fourth diffusion layer being doped with the second conductive dopant; and

g) forming a fifth diffusion layer between the fourth diffusion layer and the first diffusion layer.

6. The method of claim 5, wherein the fourth diffusion layer and the fifth diffusion layer are formed by ion injection using the same mask.

7. The method of claim 5, wherein a dopant concentration of the first diffusion layer is equal to a dopant concentration in the second diffusion layer, a dopant concentration of the third diffusion layer is higher than the dopant concentration of the first diffusion layer, a dopant concentration of the fourth diffusion layer is higher than the dopant concentration of the second diffusion layer, and a dopant concentration of the fifth diffusion layer is higher than the dopant concentration of the second diffusion layer.

8. The method of claim 5, wherein an ion injection energy for forming the first diffusion layer is larger than an ion injection energy for forming the second diffusion layer and an ion injection energy for forming the third diffusion layer is smaller than an ion injection energy for forming the second diffusion layer.

9. The method of claim 5, wherein an ion injection energy for forming the fourth diffusion layer is smaller than an ion injection energy for forming the fifth diffusion layer.