Increasing stress-enhanced drive current in a MOS transistor

• US 6,870,179 B2
• Filed: 03/31/2003
• Issued: 03/22/2005
• Est. Priority Date: 03/31/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Armstrong, Mark, Hoffmann, Thomas, Shaheed, M. Reaz, Auth, Christopher P.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Le, Thao P.
• Application Number:
  US10/404,880
• Publication Number:
  US 20040188670A1
• Time in Patent Office: 722 Days
• Field of Search: 257/18, 257/20, 257/29
• US Class Current: 257/29
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

An intentional recess or indentation is created in a region of semiconductor material that will become part of a channel of a metal oxide semiconductor (MOS) transistor structure. A layer is created on a surface of the recess to induce an appropriate type of stress in the channel.

Claims

1. A device comprising:

a region of semiconductor material that will become part of a channel of a MOS transistor structure, said region having opposing recessed portions that run along a width direction of the transistor structure; and

a strained dielectric layer in contact with and conforming to surfaces of the recessed portions.

2. The device of claim 1 further comprising:

a gate stack formed on a top surface of the region of semiconductor material, wherein the strained dielectric layer is in contact with and conforms to a top surface of the gate stack along the width direction.

3. The device of claim 2 wherein the gate stack includes a gate electrode layer on top of a gate dielectric layer.

4. The device of claim 3 wherein the gate stack further includes spacers.

5. The device of claim 2 further comprising:

an interlayer dielectric (ILD) layer in contact with and conforming to a surface of the strained dielectric layer.

6. The device of claim 5 wherein the ILD layer is thicker than the strained dielectric layer.

7. The device of claim 1 wherein the strained dielectric layer is between 500 to 2000 angstroms thick.

8. The device of claim 7 wherein horizontal surfaces of the recessed regions are between 300 and 1000 angstroms below a top surface of said semiconductor region.