Method of and apparatus for driving a dual gated MOSFET

• US 6,870,217 B2
• Filed: 10/16/2003
• Issued: 03/22/2005
• Est. Priority Date: 08/23/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Elbanhawy, Alan
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): Trinh, Hoa B.
• Application Number:
  US10/686,859
• Publication Number:
  US 20040135201A1
• Time in Patent Office: 523 Days
• Field of Search: 257/333, 257/335, 257/288, 257/340, 257/137
• US Class Current: 257/333
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/6877 the control circuit comprising active elements different from those used in the output circuit
• CPC Class Codes: H03K 2017/6878 using multi-gate field-effect transistors
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption

Abstract

A method of driving a dual-gated MOSFET having a Miller capacitance between the MOSFET gate and drain includes preparing the MOSFET to switch from a blocking mode to a conduction mode by applying to the MOSFET shielding gate a first voltage signal having a first voltage level. The first voltage level is selected to charge the Miller capacitance and thereby reduce switching losses. A second voltage signal is applied to the switching gate to switch the MOSFET from the blocking to the conduction mode. The first voltage signal is then changed to a level selected to reduce the conduction mode drain-to-source resistance and thereby reduce conduction losses. The first voltage signal is returned to the first voltage level to prepare the MOSFET for being switched from the conduction mode to the blocking mode.

Claims

1. A circuit for driving a dual-gated MOSFET, said dual-gated MOSFET being switchable between conduction and blocking modes, said dual-gated MOSFET having a shielding gate, a switching gate, a gate-to-drain overlap region, and a drain-to-source resistance when the MOSFET is in the conduction mode, said circuit comprising:

means for generating a first voltage signal for driving said shielding gate, said first voltage signal having a first voltage level for charging the gate-to-drain overlap region and a fourth voltage level for reducing the drain-to-source resistance when the MOSFET is in the conduction mode;

means for generating a second voltage signal for driving the switching gate, said second voltage signal being switchable between a low and a high voltage level; and

control means for controlling each of said means for generating to thereby switch the MOSFET between the conduction and blocking modes.

2. The circuit of claim 1, wherein said control means causes said means for generating a first voltage signal to maintain said first voltage signal at said first voltage level or bring said first voltage signal to said first voltage level at a predetermined amount of time prior to switching the MOSFET from the blocking to the conduction mode.

3. The circuit of claim 2, wherein said control means causes said means for generating said second voltage signal to be switched from said low to said high voltage level thereby causing the MOSFET to enter the conduction mode, and at a first delay time thereafter causes said first voltage signal to be switched from said first voltage level for charging the gate-to-drain overlap region to said fourth voltage level for reducing the drain-to-source resistance while the MOSFET is in the conduction mode.

4. The circuit of claim 2, wherein said control means causes said means for generating said first voltage signal to be switched from said fourth voltage level for reducing the drain-to-source resistance to said first voltage level for charging the gate-to-drain overlap region or to ground potential, and at a second delay time thereafter causes said second voltage signal to be switched from said high voltage level to said low voltage level.

5. The circuit of claim 2, wherein said first voltage level for charging the gate-to-drain overlap region is from approximately three to approximately six volts.

6. The circuit of claim 2, wherein said fourth voltage level for reducing the drain-to-source resistance is from approximately nine to approximately thirteen volts.

7. The circuit of claim 2, wherein said low voltage level of said second voltage signal is one of approximately zero volts and approximately ground potential.