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Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses

  • US 6,870,220 B2
  • Filed: 08/14/2003
  • Issued: 03/22/2005
  • Est. Priority Date: 08/23/2002
  • Status: Expired due to Term
First Claim
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1. A gate structure for a semiconductor device, said semiconductor device having a drain region, a well region and a source region, said gate structure comprising:

  • a shielding electrode, respective portions of said shielding electrode being disposed in a common plane with said drain region and said well region, a first dielectric layer disposed between said shielding electrode and said drain and well regions;

    a switching electrode, respective portions of said switching electrode being disposed in a common plane with said well region and said source region, a second dielectric layer disposed between said switching electrode and said well and source regions; and

    a third dielectric layer disposed between said shielding electrode and said switching electrode.

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