Ultra-low power basic blocks and their uses

• US 6,870,229 B2
• Filed: 06/23/2003
• Issued: 03/22/2005
• Est. Priority Date: 12/21/2000
• Status: Active Grant

• Current Assignee: Université catholique de Louvain
• Original Assignee: Université catholique de Louvain
• Inventors: Dessard, Vincent, Levacq, David, Adriaensen, Stéphane, Flandre, Denis
• Primary Examiner(s): Kang, Donghee
• Application Number:
  US10/602,016
• Publication Number:
  US 20040026760A1
• Time in Patent Office: 638 Days
• Field of Search: 361/56, 361/58, 361/91.1, 361/11, 361/117, 361/119, 257/357, 257/360, 257/364, 257/365, 327/313, 327/314, 327/325
• US Class Current: 257/360
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention relates to an ultra-low power (ULP) MOS diode. The diode has a first and a second terminal. It comprises an n-MOS transistor having a channel, a first N+ doped diffusion region at one extremity of the channel and a second N+ diffusion region at the other extremity of the channel, and a p-MOS transistor having a channel and a first P+ doped diffusion region at one extremity of the channel and a second P+ diffusion region at the other extremity of the channel. The first N+ diffusion region of the n-MOS transistor is coupled to the first P+ diffusion region of the p-MOS transistor, the gate of the n-MOS transistor is coupled to the second P+ diffusion region of the p-MOS transistor, and the gate of the p-MOS transistor is coupled to the second N+ diffusion region of the n-MOS transistor. The second P+ diffusion region of the p-MOS transistor is coupled to the first terminal of the diode and the second N+ diffusion region of the n-MOS transistor is coupled to the second terminal of the diode. The diode has a current versus voltage characteristic such that it has a negative slope in a reverse biased state of the diode.

Claims

1. A diode having a first and a second terminal, the diode comprising an n-MOS transistor having a channel, a first N+ doped diffusion region at one extremity of the channel and a second N+ diffusion region at the other extremity of the channel, and a p-MOS transistor having a channel and a first P+ doped diffusion region at one extremity of the channel and a second P+ diffusion region at the other extremity of the channel,

the first N+ diffusion region of the n-MOS transistor being coupled t the first P+ diffusion region of the p-MOS transistor,

the gate of the n-MOS transistor being coupled to the second P+ diffusion region of the p-MOS transistor, and the gate of the p-MOS transistor being coupled to the second N+ diffusion region of the n-MOS transistor, and

the second P+ diffusion region of the p-MOS transistor being coupled to the first terminal of the diode and the second N+ diffusion region of the n-MOS transistor being coupled to the second terminal of the diode,

a current versus voltage characteristic of the diode being such that it has a negative slope in a reverse biased state of the diode.

2. A diode according to claim 1, whereby the current versus voltage characteristic of the diode substantially passes through the origin of the current voltage characteristic.

3. Voltage doubler comprising two diodes coupled in series between a supply voltage node and an output node, the anode of the first diode being coupled to the supply voltage node, and the cathode of the second diode being coupled to the output node, a clock signal switching between a first and a second voltage level being applied to the node between the cathode of the first diode and the anode of the second diode, and a load capacitance being connected to the output node, whereby the two diodes are diodes according to any of claim 1 or 2.

4. Memory cell comprising two ultra-low power diodes according to claim 1 coupled in series reversely biased between a first low voltage level and a second high voltage level, the voltage level of the memory cell being present at the node between the two ultra-low power diodes.

5. Use of the memory cell of claim 4 as a level holder in domino logic.

6. Use of the memory cell of claim 4 as a level restoring device in pass gate logic.

7. Use of the memory cell of claim 4 as a data storing device in a D latch.

8. Use of the memory cell of claim 4 to maintain information on high impedance floating nodes in digital circuits.

9. Use of the memory cell of claim 4 as a level keeper device in MTCMOS circuits.

10. Electrostatic discharge protection circuit comprising a first reverse biased diode between a node to be protected and a first power supply and a second reverse biased diode between the node to be protected and a second power supply, whereby the diodes are diodes according to claim 1.