Semiconductor device utilizing dummy features to form uniform sidewall structures
First Claim
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1. A semiconductor device, comprising:
- a substrate;
a plurality of MIS transistors, each of the MIS transistors being formed on the substrate and including a gate insulating film, a gate electrode and a doped region;
a plurality of isolation regions formed in the substrate;
an interlevel dielectric film provided at least over the MIS transistors and the isolation regions;
a plurality of contact holes formed through the interlevel dielectric film, each of the contact holes reaching the doped region or the gate electrode of a corresponding one of the MIS transistors;
a plurality of dummy contact holes formed through the interlevel dielectric film to reach the isolation regions; and
sidewalls formed on side faces of the contact holes and of the dummy contact holes.
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Abstract
An inventive semiconductor device includes: a substrate; a plurality of first projections each including at least a gate electrode and formed on the substrate; and a plurality of second projections formed on the substrate. When a contour surface constituted by the uppermost face of the substrate and by side and upper faces of the first and second projections is measured for every partial area per unit area of the substrate, the maximum partial area of the contour surface is 1.6 or less times larger than the minimum partial area of the contour surface.
35 Citations
12 Claims
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1. A semiconductor device, comprising:
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a substrate;
a plurality of MIS transistors, each of the MIS transistors being formed on the substrate and including a gate insulating film, a gate electrode and a doped region;
a plurality of isolation regions formed in the substrate;
an interlevel dielectric film provided at least over the MIS transistors and the isolation regions;
a plurality of contact holes formed through the interlevel dielectric film, each of the contact holes reaching the doped region or the gate electrode of a corresponding one of the MIS transistors;
a plurality of dummy contact holes formed through the interlevel dielectric film to reach the isolation regions; and
sidewalls formed on side faces of the contact holes and of the dummy contact holes. - View Dependent Claims (2)
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3. A semiconductor device, comprising:
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a sparse region in which a plurality of first gates are arranged; and
a dense region in which a plurality of second gates are arranged more densely than the plurality of first gates in the sparse region, wherein the sparse region includes;
a first isolation region formed in a semiconductor substrate;
the plurality of first gates formed on the semiconductor substrate and including a gate insulating film and a gate electrode formed on the gate insulating film; and
a dummy gate formed on the first isolation region and having the same structure as one of the plurality of first gates, wherein the dense region includes;
a second isolation region formed in the semiconductor substrate;
the plurality of second gates formed on the semiconductor substrate, one of the plurality of second gates having a same structure as one of the plurality of first gates, wherein L-shaped sidewalls are formed on each side face of the plurality of first gates, each side face of the plurality of second gates and each side face of the dummy gate, and wherein the second isolation region has a width narrower than the first isolation region, and no dummy gate is formed on the second isolation region. - View Dependent Claims (4, 5, 6)
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7. A semiconductor device, comprising:
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a sparse region in which a plurality of first gates are arranged; and
a dense region in which a plurality of second gates are arranged more densely than the plurality of first gates in the sparse region, wherein the sparse region includes;
a first isolation region formed in a semiconductor substrate; and
the plurality of first gates formed on the semiconductor substrate and including a gate insulating film and a gate electrode formed on the gate insulating film, wherein the dense region includes;
a second isolation region formed in the semiconductor substrate;
the plurality of second gates formed on the semiconductor substrate, one of the plurality of second gates having a same structure as one of the plurality of first gates, and wherein the first isolation region is formed such that the height of the first isolation region from a surface of the semiconductor substrate is larger than that of the second isolation region from a surface of the semiconductor substrate. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification
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Current AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation), Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba Tec Corporation (Toshiba Corporation)
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Original AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
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InventorsMatsuda, Takayuki, Segawa, Mizuki
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Primary Examiner(s)Smoot, Stephen W.
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Application NumberUS10/300,798Publication NumberTime in Patent Office852 DaysField of Search257/202, 257/365, 257/508, 257/513, 257/623, 257/774, 257/775, 438/639, 438/926US Class Current257/365CPC Class CodesH01L 21/76229 Concurrent filling of a plu...H01L 21/76802 by forming openings in diel...H01L 21/76831 in via holes or trenches, e...H01L 21/823468 with a particular manufactu...H01L 21/823475 interconnection or wiring o...H01L 21/823481 isolation region manufactur...
