MTCMOS flip-flop circuit capable of retaining data in sleep mode
First Claim
1. An MTCMOS flip-flop circuit, comprising:
- a master latch unit to latch input data and output the data under the control of an internal clock;
a slave latch unit for latching input data and outputting the data under the control of an internal clock signal;
wherein an output of the flip-flop circuit retains a state just before admission to a sleep mode when the state of the system is converted from sleep mode to an active mode by means of making a data state of an input terminal of the master latch circuit into the same state as an inversed data state of an input terminal of the slave latch circuit in sleep mode and storing the data state of the input terminal of the master latch circuit.
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Abstract
The present invention relates to a flip-flop circuit employing an MTCMOS technology comprising a master latch unit and a slave latch unit, for latching input data and outputting the data under the control of an internal clock signal, wherein an output of the flip-flop circuit retains a state just before the admission to sleep mode when the state of the system is converted from sleep mode to active by means of making a data state of an input terminal of a master latch into the same state as an inversed data state of an input terminal of a slave latch circuit in sleep mode and storing it. The flip-flop circuit employing the MTCMOS technology in accordance with the present invention is capable of retaining a state just before the sleep mode when the state of the system is converted from sleep mode to active mode by using the sleep mode control signal by means of adding the feedback circuit to the conventional flip-flop circuit. In addition, while the flip-flop circuit employing the MTCMOS technology in accordance with the present invention has an operation speed slightly slower than that of the prior art flip-flop circuit employing the low-Vth transistor or the high-Vth transistor, a leakage current of the present invention is significantly smaller than that of the conventional art.
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Citations
22 Claims
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1. An MTCMOS flip-flop circuit, comprising:
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a master latch unit to latch input data and output the data under the control of an internal clock;
a slave latch unit for latching input data and outputting the data under the control of an internal clock signal;
wherein an output of the flip-flop circuit retains a state just before admission to a sleep mode when the state of the system is converted from sleep mode to an active mode by means of making a data state of an input terminal of the master latch circuit into the same state as an inversed data state of an input terminal of the slave latch circuit in sleep mode and storing the data state of the input terminal of the master latch circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An MTCMOS flip-flop circuit comprising:
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a sleep mode control circuit for receiving an external clock signal and an inverted sleep mode control signal and generating an internal clock signal;
a first inverter for inverting flip-flop input data;
a master latch gate for receiving an output signal of the first inverter and transmitting to a first node under control of the internal clock signal and the inverted internal clock signal;
a master latch circuit for receiving and latching an output signal of the master lach gate and outputting the signal to a second node;
a slave latch gate for receiving a signal of the second node and transmitting the signal to a third node under the control of the internal clock signal and the inverted clock signal;
a slave latch circuit for receiving and latching an output signal of the slave latch gate, and outputting the signal to a fourth node; and
a data retention feedback circuit for receiving a feedback input signal from the third node under control of the inverted sleep mode control signal and transmitting the feedback output signal to the first node. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification