Variable rate modulator

• US 6,870,429 B2
• Filed: 06/25/2003
• Issued: 03/22/2005
• Est. Priority Date: 04/16/1997
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Joshi, Robindra B., Liu, Huan-Chang, Hawley, Robert A.
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Chang, Joseph
• Application Number:
  US10/603,362
• Publication Number:
  US 20030231067A1
• Time in Patent Office: 636 Days
• Field of Search: 331/16, 331/47, 331/48, 375/308, 375/298
• US Class Current: 331/16
• CPC Class Codes: H04L 27/362 Modulation using more than one carrier, e.g. with quadrature carriers, separately amplitude modulated H04L27/366 takes precedence

Abstract

Clock signals and digital data signals at a variable frequency are introduced to the input of a FIFO and are passed from the FIFO at a second (or intermediate) frequency controlled by a numerically controlled oscillator. To regulate the frequency of the signals from the numerically controlled oscillator, the phases of the clock signals at the variable frequency are compared in a phase detector with the phases of the signals from the numerically controlled oscillator to generate an error signal. The error signals and the signals at a fixed sampling frequency higher than the intermediate frequency regulate the frequency of the signals from the numerically controlled oscillator and thus the frequency of the digital data signals from the FIFO. The digital data signals from the FIFO are converted to a pair of signals at the second frequency. The pair of signals at the second frequency have individual ones of a plurality of analog levels dependent upon a code indicated by successive pairs of the digital data signals. The signals at the second (or intermediate) frequency modulate a pair of trigonometrically related signals at the fixed sampling frequency. The modulated signals at the fixed sampling frequency are combined and the combined signals are sampled at the fixed sampling frequency to corresponding analog values by a digital-to-analog converter.

Claims

1. A signal processing system comprising:

an interpolator, having one or more interpolation stages, for interpolating an input data signal at a first variable frequency to generate an interpolated output signal at fixed output frequency, wherein at least one of the one or more interpolation stages interpolates by a value of M/N, where N is and integer and M is an integer or a non-integer; and

a frequency control loop coupled to the at least one of the one or more interpolation stages that interpolates by a value of M/N,

wherein the frequency control loop generates a phase offset signal proportional to M/N as a function of an offset in phase between a variable frequency clock signal at a second variable frequency and a sample clock signal at a sample clock frequency.

2. The signal processing system of claim 1, wherein the phase offset signal is greater than or equal to zero and less than one.

3. The signal processing system of claim 1, wherein the interpolator interpolates the input data signal by a non-integer value.

4. The signal processing system of claim 1 wherein the interpolator interpolates the input data signal by an integer value.

5. The signal processing system of claim 1 further comprising a modulator for modulating the interpolated output signal onto a trigonometric signal at a carrier frequency.

6. The signal processing system of claim 5 further comprising a digital to analog converter for converting the modulated signal to an analog signal.

7. The signal processing system of claim 1 wherein the frequency control loop comprises:

a phase detector that provides an error signal representing phase difference between said variable frequency clock signal at the second variable frequency and a first clock,

a loop filter coupled to said phase detector that filters said error signal,

a numerically controlled oscillator, responsive to said filtered error signal and the sample clock for providing said first clock and said phase offset signal; and

a buffer for receiving an input signal at the variable frequency and responsive to said first clock, outputting a data signal at said first clock frequency.

8. A signal processing system comprising:

a frequency control loop for providing a first clock at a first clock frequency as a function of a sample clock having a sample clock frequency and a variable frequency input clock;

a buffer for receiving an input signal at the variable frequency input clock and, responsive to said first clock, outputting a buffered signal comprising a plurality of data bits at said first clock frequency;

a symbol mapper for converting the plurality of data bits in the buffered signal to first and second data signals at said first clock frequency, wherein amplitude and phase of the first and second data signals vary to represent the binary data bits of the buffered signal; and

a first interpolator coupled to the first data signal and a second interpolator coupled to the second data signal, wherein the first and second interpolators are responsive to the first clock signal for providing first and second interpolated signals at the sample clock frequency.

9. A signal processing system comprising:

means for interpolating an input data signal at a first variable frequency to generate an interpolated output signal at fixed output frequency, wherein one or more interpolation stages of the means for interpolating interpolates by a value of M/N, where N is an integer and M is an integer or a non-integer; and

means coupled to the at least one of the one or more interpolation stages that interpolates by a value of M/N, for generating a phase offset signal proportional to M/N as a function of an offset in phase between a variable frequency clock signal at a second variable frequency and a sample clock signal at a sample clock frequency.

10. The signal processing system of claim 9 wherein the phase offset signal is greater than or equal to zero and less than one.

11. The signal processing system of claim 9 wherein the means for interpolating interpolates the input data signal by a non-integer value.

12. The signal processing system of claim 9 wherein the means for interpolating interpolates the input data signal by an integer value.

13. The signal processing system of claim 9 further comprising means for modulating the interpolated output signal onto a trigonometric signal at a carrier frequency.

14. The signal processing system of claim 13 further comprising means for converting the modulated signal to an analog signal.

15. The signal processing system of claim 9 wherein the means for generating a phase offset signal comprises:

means for generating an error signal representing phase difference between said variable frequency clock signal at the second variable frequency and a first clock,

means for filtering said error signal,

means for providing said first clock and said phase offset signal, responsive to said filtered error signal and the sample clock; and

means for receiving an input signal at the variable frequency and responsive to said first clock, outputting a data signal at said first clock frequency.