Symmetrical stacked inductor

• US 6,870,457 B2
• Filed: 08/12/2003
• Issued: 03/22/2005
• Est. Priority Date: 12/10/2002
• Status: Expired due to Fees

• Current Assignee: National Central University
• Original Assignee: National Central University
• Inventors: Chen, Wei-Zen, Chen, Wen-Hui
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Poker, Jennifer A.
• Application Number:
  US10/638,408
• Publication Number:
  US 20040108933A1
• Time in Patent Office: 588 Days
• Field of Search: 336/65, 336/83, 336/183, 336/192, 336/200, 336/206, 336/207, 336/208, 336/223, 336/232, 296/021
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind

Abstract

A symmetrical stacked inductor comprising a plurality of conductive layers using at least one conductive line formed out of a symmetrical and geometric conductive layer and having at least one inter-metal dielectric layer for isolating each conductive layer, and wherein the conductive line does not intersect; and a plurality of vias placed between the inter-metal dielectric layers for electrical conduction.

Claims

1. A symmetrically stacked inductor having at least one winding, comprising:

a plurality of conductive layers, each conductive layer including at least a pair of conductive lines defining a pair of respective portions of geometrically shaped turns of said at least one winding disposed on opposing first and second longitudinally displaced sides thereof, said portions of said turns on each said conductive layer being symmetric with respect to their position on said winding, at least a first of said plurality of conductive layers having a pair of ports formed thereon and respectively coupled to opposing ends of said at least one winding;

an inter-metal dielectric layer disposed between each adjacent pair of said plurality of conductive layers for electrically isolating said adjacent conductive layers; and

a plurality of via plugs formed in each inter-metal dielectric for layer, each via plug providing electrical connection of a conductive line on said first side of one conductive layer to a conductive line on said second side of an adjacent conductive layer.

2. The symmetrically stacked inductor of claim 1, further comprising a tapped apparatus connected to a conductive line on a second of said plurality of conductive layers.

3. The symmetrically stacked inductor of claim 1, wherein each said conductive layer includes respective portions of a pair of geometrically shaped turns for each of two windings, each said pair of portions of geometrically shaped turns being respectively disposed symmetrically on opposing first and second longitudinally displaced sides thereof to form a single chip transformer.

4. The symmetrically stacked inductor of claim 1, wherein each said conductive layer includes respective portions of a pair of geometrically shaped turns for each of three windings, each said pair of portions of geometrically shaped turns being respectively disposed symmetrically on opposing first and second longitudinally displaced sides thereof to form a single chip balun element.

5. The symmetrically stacked inductor of claim 1, wherein said geometrically shaped turn portions on one conductive layer are of a different size than said geometrically shaped turn portions on an adjacent conductive layer.

6. A symmetrically stacked inductor having at least one first winding and at least one second winding, comprising:

a plurality of first conductive layers consecutively interspersed and alternating with a plurality of second conductive layers, each of said first conductive layers including at least a pair of first conductive lines defining a pair of respective portions of geometrically shaped turns of said at least one first winding disposed symmetrically on opposing first and second longitudinally displaced sides thereof, said portions of said turns on each said first conductive layer being symmetric with respect to their position on said at least one first winding, each of said second conductive layers including at least a pair of second conductive lines defining a pair of respective portions of geometrically shaped turns of said at least one second winding disposed symmetrically on opposing first and second longitudinally displaced sides thereof, said portions of said turns on each said second conductive layer being symmetric with respect to their position on said at least one second winding, at least one of each of said plurality of first and second conductive layers having a pair of ports formed thereon and respectively coupled to opposing ends of a corresponding one of said at least one first and second windings;

an inter-metal dielectric layer separating each said first conductive layer from an adjacent second conductive layer for electrical isolation thereof;

a plurality of first via plugs formed in each inter-metal dielectric layer, each first via plug providing electrical connection of a conductive line on said first side of one first conductive layer to a conductive line on said second side of another first conductive layer; and

a plurality of second via plugs formed in each inter-metal dielectric layer, each second via plug providing electrical connection of a conductive line on said first side of one second conductive layer to a conductive line on said second side of another second conductive layer.