Video and graphics system with parallel processing of graphics windows

• US 6,870,538 B2
• Filed: 04/07/2003
• Issued: 03/22/2005
• Est. Priority Date: 11/09/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: MacInnis, Alexander G., Tang, Chengfuh Jeffrey, Xie, Xiaodong
• Primary Examiner(s): Bella, Matthew C.
• Assistant Examiner(s): Sajous, Wesner
• Application Number:
  US10/409,809
• Publication Number:
  US 20030189571A1
• Time in Patent Office: 715 Days
• Field of Search: 348/423.1, 348/558, 348/553, 348/461, 348/564, 348/569, 345/629, 345/630, 345/635, 345/636, 345501-505, 345519-522, 345/530, 345/532, 345536-538, 345/592, 345/781, 345/506
• US Class Current: 345/505
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/02 characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/024 using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/026 Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/28 : for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 : for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 : characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: H04N 11/143 : Encoding means therefor H04N11/16 takes precedence
• CPC Class Codes: H04N 11/20 : Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 : characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 : using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 : Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 21/42204 : User interfaces specially adapted for controlling a client device through a remote control device; Remote control devices therefor constructive details of casings for the remote control device H01H9/0235; user interfaces for controlling a tuning device of a television receiver through a remote control H03J9/00; remote control of peripheral devices connected to a television receiver through the remote control device of the television receiver H04B1/205
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 : for processing graphics
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/4438 : Window management, e.g. event handling following interaction with the user interface
• CPC Class Codes: H04N 21/47 : End-user applications
• CPC Class Codes: H04N 5/126 : whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/0135 : involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59
• CPC Class Codes: H04N 9/45 : Generation or recovery of colour sub-carriers
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 : Multi-standard receivers

Abstract

A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing elements process two or more graphics layers in parallel to generate blended graphics. Alpha values may be used while blending graphics. The processing elements may be integrated on an integrated circuit chip with an input for receiving the graphics data and other video and graphics components. The display engine may also include a graphics controller for receiving two or more graphics layers in parallel, for arranging the graphics layers in an order suitable for parallel processing, and for providing the arranged graphics layers to the processing elements. The blended graphics may be blended with HDTV video or SDTV video, which may be extracted from compressed data streams such as an MPEG Transport stream.

Claims

1. An integrated circuit chip comprising:

an input for receiving graphics data from a memory, the graphics data comprising a plurality of graphics images, each graphics image comprising a plurality of pixels, wherein each pixel comprises a graphics component and an alpha value;

an input for receiving a video;

a display engine comprising a plurality of processing elements capable of blending the graphics images in parallel using the alpha values to generate blended graphics, and of combining the alpha values to generate a plurality of composite alpha values; and

a video compositor capable of blending the blended graphics with the video using the composite alpha values.

2. The integrated circuit chip of claim 1, wherein the plurality of processing elements comprise at least one first processing element for blending the graphics images in parallel to generate a plurality of intermediate graphics images, and at least one second processing element for blending the plurality of intermediate graphics images to generate the blended graphics.

3. The integrated circuit chip of claim 1, further comprising:

a plurality of processing pipelines, each pipeline being capable of processing one of the plurality of graphics images to place it in a common format for blending in the plurality of processing elements.

4. A video and graphics system comprising:

a display engine comprising;

an input for receiving data representing graphics from a memory, wherein the data representing graphics defines a plurality of graphics windows;

at least one first processing element for blending the plurality of graphics windows in parallel to generate a plurality of intermediate graphics images; and

at least one second processing element for blending the plurality of intermediate graphics images to generate a blended graphics image.

5. The video and graphics system of claim 4, further comprising:

a plurality of processing pipelines, each pipeline being capable of processing one of the plurality of graphics windows to place it in a common format for blending in the processing elements.

6. The video and graphics system of claim 4, wherein the system is integrated on an integrated circuit chip.

7. The video and graphics system of claim 5, further comprising:

a graphics controller f or receiving the plurality of graphics windows in parallel from the processing pipelines, for arranging the graphics windows in an order suitable for parallel processing, and for providing the arranged graphics windows to the at least one first processing element.

8. The video and graphics system of claim 7, wherein each processing pipeline comprises a graphics converter for converting the format of one of the plurality of graphics windows to the common format, and for providing it to the graphics controller.

9. The video and graphics system of claim 4, wherein a plurality of alpha values are used to blend the plurality of graphics windows to generate the plurality of intermediate graphics images.

10. The video and graphics system of claim 9, wherein the plurality of alpha values include at least one alpha value per each of the plurality of graphics windows.

11. The video and graphics system of claim 10, wherein each graphics window comprises a plurality of pixels, and wherein the plurality of alpha values comprise at least one alpha value per each of the plurality of pixels.

13. The video and graphics system of claim 4, further comprising a video compositor for compositing the blended graphics image with a video image to generate a composited video and graphics image.

12. A video and graphics system comprising:

a display engine comprising;

an input for receiving data representing graphics from a memory, wherein the data representing graphics defines a plurality of graphics windows;

at least one first processing element for blending the plurality of graphics windows in parallel to generate a plurality of intermediate graphics images; and

at least one second processing element for blending the plurality of intermediate graphics images to generate a blended graphics image,

wherein the at least one first processing element comprises two first graphics blenders, the at least one second processing element comprises a second graphics blender, and wherein at least two graphics windows are blended together in each of the two first graphics blenders in parallel to generate one of the intermediate graphics images, and the intermediate graphics images are provided to the second graphics blender for blending the intermediate graphics images to generate the blended graphics image.

14. A method of blending a plurality of graphics windows to generate a blended graphics image, comprising:

receiving data representing graphics, the data representing graphics defining the plurality of graphics windows;

blending the plurality of graphics windows in parallel to generate a plurality of intermediate graphics images; and

blending the plurality of intermediate graphics images to generate the blended graphics image.

15. The method of claim 14, further comprising processing the graphics windows to place them in a common format for blending.

16. The method of claim 14, further comprising arranging the graphics windows in an order suitable for parallel processing.

17. The method of claim 14, wherein blending the plurality of graphics windows in parallel comprises blending the plurality of graphics windows in parallel using a plurality of alpha values.

18. The method of claim 17 wherein the plurality of alpha values include at least one alpha value per each of the plurality of graphics windows.

19. The method of claim 18 wherein each of the plurality of graphics windows comprises a plurality of pixels, and the plurality of alpha values comprise at least one alpha value per each of the plurality of pixels.

20. The method of claim 14, further comprising compositing the blended graphics image with a video image to generate a composited video and graphics image.