Electron spin mechanisms for inducing magnetic-polarization reversal

• US 6,870,762 B2
• Filed: 11/19/2003
• Issued: 03/22/2005
• Est. Priority Date: 09/27/2001
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hannah, Eric C., Brown, Michael A.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US10/717,954
• Publication Number:
  US 20040100820A1
• Time in Patent Office: 489 Days
• Field of Search: 365/173, 365/171, 365/158, 365/97, 365/66, 365/48
• US Class Current: 365/173
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: H01F 10/1936 Half-metallic, e.g. epitaxial CrO2 or NiMnSb films
• CPC Class Codes: H01F 10/3254 the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: Y10T 428/24843 with heat sealable or heat releasable adhesive layer

Abstract

An apparatus includes a low magnetic-coercivity layer of material (LMC layer) having a majority electron-spin-polarization (M-ESP), an energy-gap coupled with the LMC layer, wherein a flow of spin-polarized electrons having an electron-spin-polarization anti-parallel to the LMC layer are injected via the energy-gap, to change the M-ESP of the LMC layer. A non-magnetic material is in electrical communication with the LMC layer and provides a spin-balanced source of current to the LMC layer, responsive to the injection of spin-polarized electrons into the LMC layer.

Claims

1. An energy-gap apparatus comprising:

a first magnetic mirror (MM);

a second magnetic mirror (MM); and

a conductive layer of material disposed between said first MM and said second MM to magnetically decouple said first MM from said second MM.

2. The apparatus of claim 1, wherein said first MM is a half-metallic.

3. The apparatus of claim 1, wherein said second MM is a half-metallic.

4. The apparatus of claim 1, further comprising:

a low magnetic-coercivity layer of material (LMC layer), having a majority electron-spin-polarization (M-ESP), said first MM having an ESP parallel to said M-ESP or said LMC layer, wherein said first MM is configured to substantially allow electrons having an ESP parallel to said ESP of said first MM to pass through said first MM and to substantially prevent electrons having an ESP anti-parallel to said ESP of said first MM (anti-parallel electrons) from passing through said first MM, said first MM coupled with said LMC layer; and

a high magnetic-coercivity layer of material (HMC layer), having a M-ESP, said second MM having an ESP parallel to said M-ESP of said HMC layer, wherein said second MM is configured to substantially allow electrons having an ESP parallel to said ESP of said second MM to pass through said second MM and to substantially prevent electrons having an ESP anti-parallel to said ESP of said second MM from passing through said second MM, said second MM coupled with said HMC layer.

5. The apparatus of claim 4, wherein said first MM is configured to cause an accumulation of the anti-parallel electrons to interact with and change said M-ESP of said LMC layer.

6. The apparatus of claim 5, wherein said ESP of said first MM is configured to change with said M-ESP of said LMC layer.

7. The apparatus of claim 4, wherein a first impedance may be measured between said LMC layer and said HMC layer when said M-ESP of said LMC layer and said M-ESP of said HMC layer are parallel.

8. The apparatus of claim 7, wherein a second impedance may be measured between said LMC layer and said HMC layer when said M-ESP of said LMC layer and said M-ESP of said HMC layer are anti-parallel.

9. The apparatus of claim 8, wherein said second impedance is larger than said first impedance.

10. The apparatus of claim 8, wherein said first impedance corresponds with a first memory state of a memory cell and said second impedance corresponds with a second memory state of said memory cell.

11. The apparatus of claim 1, further comprising:

a low magnetic-coercivity layer of material (LMC layer), having a majority electron spin polarization (M-ESP) parallel with an electron-spin-polarization (ESP) of said first MM; and

a high magnetic coercivity layer of material (HMC layer), having a fixed M-ESP, said second MM having an ESP parallel with said fixed M-ESP of said HMC layer.

12. The apparatus of claim 11, wherein a flow of spin-polarized electrons having an ESP anti-parallel to said M-ESP of said LMC layer may be injected from said HMC layer to said LMC layer to cause an accumulation of the spin-polarized electrons to interact with and change said M-ESP of said LMC layer.

13. The apparatus of claim 12, wherein said ESP of said first MM is configured to change with said M-ESP of said LMC layer.

14. A method, comprising:

providing a first magnetic mirror (MM);

providing a second magnetic mirror (MM); and

magnetically decoupling the first MM from the second MM with a conductive layer of material disposed between the first MM and the second MM.

15. The method of claim 14, wherein said first MM is a half-metallic.

16. The method of claim 14, wherein said second MM is a half-metallic.

17. The method of claim 14, further comprising:

coupling the first MM with a low magnetic-coercivity layer of material (LMC layer) having a majority electron-spin-polarization (M-ESP), the first MM having an ESP parallel to said M-ESP of the LMC layer, wherein the first MM is configured to substantially allow electrons having an ESP parallel to said ESP of the first MM to pass through the first MM and to substantially prevent electrons having an ESP anti-parallel to the ESP of the first MM (anti-parallel electrons) from passing through the first MM; and

coupling the second MM with a high magnetic-coercivity layer of material (HMC layer), having a M-ESP, the second MM having an ESP parallel to the M-ESP of the HMC layer, wherein the second MM is configured to substantially allow electrons having an ESP parallel to the ESP of the second MM to pass through the second MM and to substantially prevent electrons having an ESP anti-parallel to the ESP of the second MM from passing through the second MM.

18. The method of claim 17, wherein the first MM is configured to cause an accumulation of the anti-parallel electrons to interact with and change the M-ESP of the LMC layer.

19. The method of claim 18, wherein the ESP of the first MM is configured to change with the M-ESP of the LMC layer.

20. The method of claim 17, further comprising:

measuring a first impedance between the LMC layer and the HMC layer when the M-ESP of the LMC layer and the M-ESP of the HMC layer are parallel.

21. The method of claim 20, further comprising:

measuring a second impedance between the LMC layer and the HMC layer when the M-ESP of the LMC layer and the M-ESP of the HMC layer are anti-parallel.

22. The method of claim 21, wherein the second impedance is larger than the first impedance.

23. The method of claim 21, wherein the first impedance corresponds with a first memory state of a memory cell and the second impedance corresponds with a second memory state of the memory cell.

24. The method of claim 14, further comprising:

providing a low magnetic-coercivity layer of material (LMC layer), having a majority electron-spin-polarization (M-ESP) parallel with an electron-spin-polarization (ESP) of the first MM; and

providing a high magnetic coercivity layer of material (HMC layer), having a fixed M-ESP, the second MM having an ESP parallel with the fixed M-ESP of the HMC layer.

25. The method of claim 24, further comprising:

injecting a flow of spin-polarized electrons having an ESP anti-parallel to the M-ESP of the LMC layer from the HMC layer to the LMC layer to cause an accumulation of the spin-polarized electrons to interact with and change the M-ESP of the LMC layer.

26. The method of claim 25, wherein the ESP of the first MM is configured to change with the M-ESP of the LMC layer.

27. A system, comprising:

a processor; and

a magnetic random access memory (MRAM) coupled with the processor, the MRAM comprising;

a first magnetic mirror (MM);

a second magnetic mirror (MM); and

a conductive layer of material disposed between the first MM and the second MM to magnetically decouple the first MM from the second MM.

28. The system of claim 27, further comprising:

an MRAM controller coupled with the processor and the MRAM, wherein the MRAM controller is configured to store data in the MRAM and to read data from the MRAM.

29. The system of claim 28, further comprising:

a system bus coupled with the processor; and

a display coupled with the system bus.

30. The system of claim 27, further comprising:

a low magnetic-coercivity layer of material (LMC layer) coupled to the first MM, the LMC layer having a majority electron-spin-polarization (M-ESP) parallel with an electron-spin-polarization (ESP) of the first MM; and

a high magnetic coercivity layer of material (HMC layer) coupled to the second MM, the HMC layer having a fixed M-ESP, the second MM having an ESP parallel with the fixed M-ESP of the HMC layer.

31. The system of claim 30, wherein a flow of spin-polarized electrons having an ESP anti-parallel to the M-ESP of the LMC layer may be injected from the HMC layer to the LMC layer to cause an accumulation of the spin-polarized electrons to interact with and change the M-ESP of the LMC layer.

32. The system of claim 30, wherein the first MM is configured to substantially allow electrons having an ESP parallel to the ESP of the first MM to pass through the first MM and to substantially prevent electrons having an ESP anti-parallel to the ESP of the first MM (anti-parallel electrons) from passing through the first MM.

and wherein the second MM is configured to substantially allow electrons having an ESP parallel to the ESP of the second MM to pass through the second MM and to substantially prevent electrons having an ESP anti-parallel to the ESP of the second MM from passing through the second MM.

33. The system of claim 30, wherein a first impedance may be measured between the LMC layer and the HMC layer when the M-ESP of the LMC layer and the M-ESP of the HMC layer are parallel.

34. The system of claim 33, wherein a second impedance may be measured between the LMC layer and the HMC layer when the M-ESP of the LMC layer and the M-ESP of the HMC layer are anti-parallel.

35. The system of claim 34, wherein the first impedance corresponds with a first memory state of a memory cell in the MRAM and the second impedance corresponds with a second memory state of the memory cell.